/********************************************************************
* Copyright (C) 2011-2018 Texas Instruments Incorporated.
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
/*********************************************************************
* file: cslr_bootcfg.h
*
* Brief: This file contains the Register Description for bootcfg
*
*********************************************************************/
#ifndef CSLR_BOOTCFG_V2_H
#define CSLR_BOOTCFG_V2_H

/* CSL Modification:
 *  The file has been modified from the AUTOGEN file for the following
 *  reasons:-
 *      a) Header files are included as per RTSC guidelines
 *      b) Changed BOOTADDR_GEM0_REG-BOOTADDR_GEM3_REG to an array BOOTADDR_GEM_REG[4]
 *      c) Changed RSTMUX0-RSTMUX9 to an array RSTMUX[10]
 *      d) Changed NMIGR_0-NMIGR_3 to an array NMIGR[4]
 *      e) Changed IPCGR0-IPCGR9 to an array IPCGR[10]
 *      f) Changed IPCAR0-IPCAR9 to an array IPCAR[10]
 *      g) Updated main/pa/ddr3a/arm PLLC definitions
 */

#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>

#ifdef __cplusplus
extern "C" {
#endif

/* Minimum unit = 1 byte */

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 REVISION_REG;
    volatile Uint8 RSVD0[4];
    volatile Uint32 DIE_ID_REG0;
    volatile Uint32 DIE_ID_REG1;
    volatile Uint32 DIE_ID_REG2;
    volatile Uint32 DIE_ID_REG3;
    volatile Uint32 JTAG_ID_REG0;
    volatile Uint8 RSVD1[4];
    volatile Uint32 DEVSTAT;
    volatile Uint8 RSVD2[20];
    volatile Uint32 KICK_REG0;
    volatile Uint32 KICK_REG1;
    volatile Uint8 RSVD3[4];
#ifdef CSL_MODIFICATION
    volatile Uint32 BOOTADDR_GEM0_REG;
    volatile Uint32 BOOTADDR_GEM1_REG;
    volatile Uint32 BOOTADDR_GEM2_REG;
    volatile Uint32 BOOTADDR_GEM3_REG;
#else
    volatile Uint32 BOOTADDR_GEM_REG[4];
#endif
    volatile Uint8 RSVD4[140];
    volatile Uint32 INTR_RAW_STATUS_REG; /* This gives the raw interrupt status for reads and allows setting of interrupts for writes */
    volatile Uint32 INTR_ENABLED_STATUS_REG; /* This gives the enabled interrupt status for reads and allows clearing of interrupts for writes */
    volatile Uint32 INTR_ENABLE_REG; /* Contains the interrupt enables on reads and allows setting on writes */
    volatile Uint32 INTR_ENABLE_CLR_REG; /* Contains the interrupt enables on reads and allows clearing on writes */
    volatile Uint32 EOI_REG; /* The End of Interrupt write declares a serviced interrupt */
    volatile Uint32 FAULT_ADDRESS_REG; /* This holds the address of the reported fault */
    volatile Uint32 FAULT_STATUS_REG; /* This holds the parameters and status of a fault */
    volatile Uint32 FAULT_CLEAR_REG; /* This allows clearing of the current fault with a write of 1 */
    volatile Uint8 RSVD5[16];
    volatile Uint32 MAC_ID0;
    volatile Uint32 MAC_ID1;
    volatile Uint8 RSVD6[16];
    volatile Uint32 PCIEVENDORID;
    volatile Uint32 DISABLESTAT; /* Disable Status */
    volatile Uint32 LRSTNMISTAT_CLR;
    volatile Uint32 RESET_STAT_CLR;
    volatile Uint8 RSVD7[4];
    volatile Uint32 BOOT_COMPLETE;
    volatile Uint32 BOOT_PROGRESS;
    volatile Uint32 RESET_STAT;
    volatile Uint32 LRSTNMISTAT;
    volatile Uint32 DEVCFG;
    volatile Uint32 PWR_STAT;
    volatile Uint32 UART0_DISABLE; /* Disable UART0 */
    volatile Uint32 UART1_DISABLE; /* Disable UART1 */
    volatile Uint32 UART2_DISABLE; /* Disable UART2 */
    volatile Uint32 UART3_DISABLE; /* Disable UART3 */
    volatile Uint32 USB_DISABLE; /* Disable USB */
    volatile Uint8 RSVD8[40];
    volatile Uint32 SEN0_0_EFUSE_REG0;
    volatile Uint32 SEN1_0_EFUSE_REG1;
    volatile Uint32 SEN2_0_EFUSE_REG2;
    volatile Uint32 SEN3_0_EFUSE_REG3;
    volatile Uint32 SEN0_1_EFUSE_REG4;
    volatile Uint32 SEN1_1_EFUSE_REG5;
    volatile Uint32 SEN2_1_EFUSE_REG6;
    volatile Uint32 SEN3_1_EFUSE_REG7;
    volatile Uint32 SEN0_2_EFUSE_REG8;
    volatile Uint32 SEN1_2_EFUSE_REG9;
    volatile Uint32 SEN2_2_EFUSE_REG10;
    volatile Uint32 SEN3_2_EFUSE_REG11;
    volatile Uint32 SEN0_3_EFUSE_REG12;
    volatile Uint32 SEN1_3_EFUSE_REG13;
    volatile Uint32 SEN2_3_EFUSE_REG14;
    volatile Uint32 SEN3_3_EFUSE_REG15;
    volatile Uint8 RSVD9[48];
#ifdef CSL_MODIFICATION
    volatile Uint32 NMIGR_0;
    volatile Uint32 NMIGR_1;
    volatile Uint32 NMIGR_2;
    volatile Uint32 NMIGR_3;
#else
    volatile Uint32 NMIGR[4];
#endif
    volatile Uint8 RSVD10[48];
#ifdef CSL_MODIFICATION
    volatile Uint32 IPCGR0;
    volatile Uint32 IPCGR1;
    volatile Uint32 IPCGR2;
    volatile Uint32 IPCGR3;
    volatile Uint8 RSVD11[16];
    volatile Uint32 IPCGR8;
    volatile Uint32 IPCGR9;
#else
    volatile Uint32 IPCGR[10];
#endif
    volatile Uint8 RSVD12[20];
    volatile Uint32 IPCGRH;
#ifdef CSL_MODIFICATION
    volatile Uint32 IPCAR0;
    volatile Uint32 IPCAR1;
    volatile Uint32 IPCAR2;
    volatile Uint32 IPCAR3;
    volatile Uint8 RSVD13[16];
    volatile Uint32 IPCAR8;
    volatile Uint32 IPCAR9;
#else
    volatile Uint32 IPCAR[10];
#endif
    volatile Uint8 RSVD14[20];
    volatile Uint32 IPCARH;
    volatile Uint8 RSVD15[24];
    volatile Uint32 TINPSEL0;
    volatile Uint8 RSVD16[4];
    volatile Uint32 TINPSEL2;
    volatile Uint32 TINPSEL3;
    volatile Uint32 TINPSEL4;
    volatile Uint8 RSVD17[12];
    volatile Uint32 TOUTPSEL0;
    volatile Uint32 TOUTPSEL1;
    volatile Uint32 USB_EBC_IN_CTL;
    volatile Uint8 RSVD18[4];
#ifdef CSL_MODIFICATION
    volatile Uint32 RSTMUX0;
    volatile Uint32 RSTMUX1;
    volatile Uint32 RSTMUX2;
    volatile Uint32 RSTMUX3;
    volatile Uint8 RSVD19[16];
    volatile Uint32 RSTMUX8;
    volatile Uint32 RSTMUX9;
#else
    volatile Uint32 RSTMUX[10];
#endif
    volatile Uint8 RSVD20[32];
    volatile Uint32 MAIN_PLL_CTL0;
    volatile Uint32 MAIN_PLL_CTL1;
    volatile Uint32 PASS_PLL_CTL0;
    volatile Uint32 PASS_PLL_CTL1;
    volatile Uint32 DDRA_PLL_CTL0;
    volatile Uint32 DDRA_PLL_CTL1;
    volatile Uint8 RSVD21[8];
    volatile Uint32 ARM_PLL_CTL0;
    volatile Uint32 ARM_PLL_CTL1;
    volatile Uint32 DFE_PLL_CTL0;
    volatile Uint32 DFE_PLL_CTL1;
    volatile Uint8 RSVD22[28];
    volatile Uint32 SECURE_CONTROL;
    volatile Uint8 RSVD23[96];
    volatile Uint32 ARMENDIAN_CFG0_0;
    volatile Uint32 ARMENDIAN_CFG0_1;
    volatile Uint32 ARMENDIAN_CFG0_2;
    volatile Uint8 RSVD24[4];
    volatile Uint32 ARMENDIAN_CFG1_0;
    volatile Uint32 ARMENDIAN_CFG1_1;
    volatile Uint32 ARMENDIAN_CFG1_2;
    volatile Uint8 RSVD25[4];
    volatile Uint32 ARMENDIAN_CFG2_0;
    volatile Uint32 ARMENDIAN_CFG2_1;
    volatile Uint32 ARMENDIAN_CFG2_2;
    volatile Uint8 RSVD26[4];
    volatile Uint32 ARMENDIAN_CFG3_0;
    volatile Uint32 ARMENDIAN_CFG3_1;
    volatile Uint32 ARMENDIAN_CFG3_2;
    volatile Uint8 RSVD27[4];
    volatile Uint32 ARMENDIAN_CFG4_0;
    volatile Uint32 ARMENDIAN_CFG4_1;
    volatile Uint32 ARMENDIAN_CFG4_2;
    volatile Uint8 RSVD28[4];
    volatile Uint32 ARMENDIAN_CFG5_0;
    volatile Uint32 ARMENDIAN_CFG5_1;
    volatile Uint32 ARMENDIAN_CFG5_2;
    volatile Uint8 RSVD29[4];
    volatile Uint32 ARMENDIAN_CFG6_0;
    volatile Uint32 ARMENDIAN_CFG6_1;
    volatile Uint32 ARMENDIAN_CFG6_2;
    volatile Uint8 RSVD30[4];
    volatile Uint32 ARMENDIAN_CFG7_0;
    volatile Uint32 ARMENDIAN_CFG7_1;
    volatile Uint32 ARMENDIAN_CFG7_2;
    volatile Uint8 RSVD31[476];
    volatile Uint32 SPARE_2;
    volatile Uint32 SPARE_3;
    volatile Uint32 SPARE_4;
    volatile Uint32 SPARE_5;
    volatile Uint32 SPARE_6;
    volatile Uint32 SPARE_7;
    volatile Uint32 SPARE_8;
    volatile Uint32 SPARE_9;
    volatile Uint32 SPARE_10;
    volatile Uint32 SPARE_11;
    volatile Uint32 SPARE_12;
    volatile Uint32 SPARE_13;
    volatile Uint32 SPARE_14;
    volatile Uint32 SPARE_15;
    volatile Uint32 PIN_MUXCTL0;
    volatile Uint32 PIN_MUXCTL1;
    volatile Uint32 PIN_MUXCTL2;
    volatile Uint8 RSVD32[76];
    volatile Uint32 DFE_CLKDIV_CTL;
    volatile Uint32 DFE_CLKSYNC_CTL;
    volatile Uint8 RSVD33[8];
    volatile Uint32 IQN_AILRSTISO_CTL;
    volatile Uint32 IQN_RSTREQ_CTL;
    volatile Uint32 CHIP_MISC;
    volatile Uint8 RSVD34[4];
    volatile Uint32 SPARE_0;
    volatile Uint32 SPARE_1;
    volatile Uint32 SYSENDSTAT;
    volatile Uint32 PLLLOCK_PINCTL;
    volatile Uint32 PLLLOCK_STAT;
    volatile Uint32 PLLLOCK_EVAL;
    volatile Uint32 PLLCLKSEL_STAT;
    volatile Uint8 RSVD35[12];
    volatile Uint32 TSRXCLK_PINCTL;
    volatile Uint8 RSVD36[1228];
    volatile Uint32 LED_CORE_PASSDONE0;
    volatile Uint32 LED_CORE_PASSDONE1;
    volatile Uint8 RSVD37[24];
    volatile Uint32 LED_ARM_BOOTADDR;
    volatile Uint8 RSVD38[12];
    volatile Uint32 LED_GPIO_CLR;
    volatile Uint32 LED_GPIO_CLR1;
    volatile Uint32 LED_GPIO;
    volatile Uint32 LED_GPIO1;
    volatile Uint32 LED_PLLLOCK0;
    volatile Uint32 LED_PLLLOCK1;
    volatile Uint32 LED_CHIP_PASSDONE;
    volatile Uint8 RSVD39[4];
    volatile Uint32 TDIODE;
    volatile Uint32 MARGIN0;
    volatile Uint32 MARGIN1;
    volatile Uint32 MARGIN2;
    volatile Uint8 RSVD40[16];
    volatile Uint32 INT_SPARE0;
    volatile Uint32 INT_SPARE1;
    volatile Uint32 LED_MISC_CTL;
    volatile Uint32 CHIP_MISC_CTL1;
    volatile Uint32 OBSCLK_CTL;
    volatile Uint32 INT_DISABLESTAT;
    volatile Uint8 RSVD41[8];
    volatile Uint32 EFUSE_RSVD0;
    volatile Uint32 EFUSE_RSVD1;
    volatile Uint32 EFUSE_RSVD2;
    volatile Uint32 EFUSE_RSVD3;
    volatile Uint32 PWRSWTCH_WKUP_MODE0_0;
    volatile Uint32 PWRSWTCH_WKUP_MODE0_1;
    volatile Uint32 PWRSWTCH_WKUP_MODE1_0;
    volatile Uint32 PWRSWTCH_WKUP_MODE1_1;
    volatile Uint32 INT_PIN_MUXCTL;
} CSL_BootcfgRegs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* revision_reg */

#define CSL_BOOTCFG_REVISION_REG_REV_SCHEME_MASK (0xC0000000u)
#define CSL_BOOTCFG_REVISION_REG_REV_SCHEME_SHIFT (0x0000001Eu)
#define CSL_BOOTCFG_REVISION_REG_REV_SCHEME_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_REVISION_REG_REV_MODULE_MASK (0x0FFF0000u)
#define CSL_BOOTCFG_REVISION_REG_REV_MODULE_SHIFT (0x00000010u)
#define CSL_BOOTCFG_REVISION_REG_REV_MODULE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_REVISION_REG_REV_RTL_MASK (0x0000F800u)
#define CSL_BOOTCFG_REVISION_REG_REV_RTL_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_REVISION_REG_REV_RTL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_REVISION_REG_REV_MAJOR_MASK (0x00000700u)
#define CSL_BOOTCFG_REVISION_REG_REV_MAJOR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_REVISION_REG_REV_MAJOR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_REVISION_REG_REV_CUSTOM_MASK (0x000000C0u)
#define CSL_BOOTCFG_REVISION_REG_REV_CUSTOM_SHIFT (0x00000006u)
#define CSL_BOOTCFG_REVISION_REG_REV_CUSTOM_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_REVISION_REG_REV_MINOR_MASK (0x0000003Fu)
#define CSL_BOOTCFG_REVISION_REG_REV_MINOR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_REVISION_REG_REV_MINOR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_REVISION_REG_RESETVAL (0x00000000u)

/* die_id_reg0 */

#define CSL_BOOTCFG_DIE_ID_REG0_DIE_ID0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DIE_ID_REG0_DIE_ID0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DIE_ID_REG0_DIE_ID0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DIE_ID_REG0_RESETVAL (0x00000000u)

/* die_id_reg1 */

#define CSL_BOOTCFG_DIE_ID_REG1_DIE_ID1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DIE_ID_REG1_DIE_ID1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DIE_ID_REG1_DIE_ID1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DIE_ID_REG1_RESETVAL (0x00000000u)

/* die_id_reg2 */

#define CSL_BOOTCFG_DIE_ID_REG2_DIE_ID2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DIE_ID_REG2_DIE_ID2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DIE_ID_REG2_DIE_ID2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DIE_ID_REG2_RESETVAL (0x00000000u)

/* die_id_reg3 */

#define CSL_BOOTCFG_DIE_ID_REG3_DIE_ID3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DIE_ID_REG3_DIE_ID3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DIE_ID_REG3_DIE_ID3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DIE_ID_REG3_RESETVAL (0x00000000u)

/* jtag_id_reg0 */

#define CSL_BOOTCFG_JTAG_ID_REG0_LSBFIELD_MASK (0x00000001u)
#define CSL_BOOTCFG_JTAG_ID_REG0_LSBFIELD_SHIFT (0x00000000u)
#define CSL_BOOTCFG_JTAG_ID_REG0_LSBFIELD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_JTAG_ID_REG0_MANUFACTURERID_MASK (0x00000FFEu)
#define CSL_BOOTCFG_JTAG_ID_REG0_MANUFACTURERID_SHIFT (0x00000001u)
#define CSL_BOOTCFG_JTAG_ID_REG0_MANUFACTURERID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_JTAG_ID_REG0_PARTID_MASK (0x0FFFF000u)
#define CSL_BOOTCFG_JTAG_ID_REG0_PARTID_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_JTAG_ID_REG0_PARTID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_JTAG_ID_REG0_VARIANT_MASK (0xF0000000u)
#define CSL_BOOTCFG_JTAG_ID_REG0_VARIANT_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_JTAG_ID_REG0_VARIANT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_JTAG_ID_REG0_RESETVAL (0x00000000u)

/* devstat */

#define CSL_BOOTCFG_DEVSTAT_LENDIAN_MASK (0x00000001u)
#define CSL_BOOTCFG_DEVSTAT_LENDIAN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DEVSTAT_LENDIAN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_BOOTMODE_MASK (0x0001FFFEu)
#define CSL_BOOTCFG_DEVSTAT_BOOTMODE_SHIFT (0x00000001u)
#define CSL_BOOTCFG_DEVSTAT_BOOTMODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_AVSIFSEL_MASK (0x00000000u)
#define CSL_BOOTCFG_DEVSTAT_AVSIFSEL_SHIFT (0x00000012u)
#define CSL_BOOTCFG_DEVSTAT_AVSIFSEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_MAINPLL_OD_SEL_MASK (0x00080000u)
#define CSL_BOOTCFG_DEVSTAT_MAINPLL_OD_SEL_SHIFT (0x00000013u)
#define CSL_BOOTCFG_DEVSTAT_MAINPLL_OD_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_ARM_BENDIAN_MASK (0x00400000u)
#define CSL_BOOTCFG_DEVSTAT_ARM_BENDIAN_SHIFT (0x00000016u)
#define CSL_BOOTCFG_DEVSTAT_ARM_BENDIAN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_DDR3A_MAP_EN_MASK (0x02000000u)
#define CSL_BOOTCFG_DEVSTAT_DDR3A_MAP_EN_SHIFT (0x00000019u)
#define CSL_BOOTCFG_DEVSTAT_DDR3A_MAP_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_CSISC2_0_MUXSEL_MASK (0x04000000u)
#define CSL_BOOTCFG_DEVSTAT_CSISC2_0_MUXSEL_SHIFT (0x0000001Au)
#define CSL_BOOTCFG_DEVSTAT_CSISC2_0_MUXSEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_CSISC2_CLKCTL_MASK (0x08000000u)
#define CSL_BOOTCFG_DEVSTAT_CSISC2_CLKCTL_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_DEVSTAT_CSISC2_CLKCTL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_RESETVAL     (0x00000000u)

/* kick_reg0 */

#define CSL_BOOTCFG_KICK_REG0_KICK0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_KICK_REG0_KICK0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_KICK_REG0_KICK0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_KICK_REG0_RESETVAL   (0x00000000u)

/* kick_reg1 */

#define CSL_BOOTCFG_KICK_REG1_KICK1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_KICK_REG1_KICK1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_KICK_REG1_KICK1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_KICK_REG1_RESETVAL   (0x00000000u)

/* bootaddr_gem0_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_BOOTADDR_GEM0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_BOOTADDR_GEM0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_BOOTADDR_GEM0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_RESETVAL (0x00000000u)

/* bootaddr_gem1_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM1_REG_BOOTADDR_GEM1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_BOOTADDR_GEM1_REG_BOOTADDR_GEM1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM1_REG_BOOTADDR_GEM1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOTADDR_GEM1_REG_RESETVAL (0x00000000u)

/* bootaddr_gem2_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM2_REG_BOOTADDR_GEM2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_BOOTADDR_GEM2_REG_BOOTADDR_GEM2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM2_REG_BOOTADDR_GEM2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOTADDR_GEM2_REG_RESETVAL (0x00000000u)

/* bootaddr_gem3_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM3_REG_BOOTADDR_GEM3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_BOOTADDR_GEM3_REG_BOOTADDR_GEM3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM3_REG_BOOTADDR_GEM3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOTADDR_GEM3_REG_RESETVAL (0x00000000u)

/* intr_raw_status_reg */

#define CSL_BOOTCFG_INTR_RAW_STATUS_REG_ADDR_ERR_MASK (0x00000002u)
#define CSL_BOOTCFG_INTR_RAW_STATUS_REG_ADDR_ERR_SHIFT (0x00000001u)
#define CSL_BOOTCFG_INTR_RAW_STATUS_REG_ADDR_ERR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INTR_RAW_STATUS_REG_PROT_ERR_MASK (0x00000001u)
#define CSL_BOOTCFG_INTR_RAW_STATUS_REG_PROT_ERR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_INTR_RAW_STATUS_REG_PROT_ERR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INTR_RAW_STATUS_REG_RESETVAL (0x00000000u)

/* intr_enabled_status_reg */

#define CSL_BOOTCFG_INTR_ENABLED_STATUS_REG_ENABLED_ADDR_ERR_MASK (0x00000002u)
#define CSL_BOOTCFG_INTR_ENABLED_STATUS_REG_ENABLED_ADDR_ERR_SHIFT (0x00000001u)
#define CSL_BOOTCFG_INTR_ENABLED_STATUS_REG_ENABLED_ADDR_ERR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INTR_ENABLED_STATUS_REG_ENABLED_PROT_ERR_MASK (0x00000001u)
#define CSL_BOOTCFG_INTR_ENABLED_STATUS_REG_ENABLED_PROT_ERR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_INTR_ENABLED_STATUS_REG_ENABLED_PROT_ERR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INTR_ENABLED_STATUS_REG_RESETVAL (0x00000000u)

/* intr_enable_reg */

#define CSL_BOOTCFG_INTR_ENABLE_REG_ADDR_ERR_EN_MASK (0x00000002u)
#define CSL_BOOTCFG_INTR_ENABLE_REG_ADDR_ERR_EN_SHIFT (0x00000001u)
#define CSL_BOOTCFG_INTR_ENABLE_REG_ADDR_ERR_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INTR_ENABLE_REG_PROT_ERR_EN_MASK (0x00000001u)
#define CSL_BOOTCFG_INTR_ENABLE_REG_PROT_ERR_EN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_INTR_ENABLE_REG_PROT_ERR_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INTR_ENABLE_REG_RESETVAL (0x00000000u)

/* intr_enable_clr_reg */

#define CSL_BOOTCFG_INTR_ENABLE_CLR_REG_ADDR_ERR_EN_CLR_MASK (0x00000002u)
#define CSL_BOOTCFG_INTR_ENABLE_CLR_REG_ADDR_ERR_EN_CLR_SHIFT (0x00000001u)
#define CSL_BOOTCFG_INTR_ENABLE_CLR_REG_ADDR_ERR_EN_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INTR_ENABLE_CLR_REG_PROT_ERR_EN_CLR_MASK (0x00000001u)
#define CSL_BOOTCFG_INTR_ENABLE_CLR_REG_PROT_ERR_EN_CLR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_INTR_ENABLE_CLR_REG_PROT_ERR_EN_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INTR_ENABLE_CLR_REG_RESETVAL (0x00000000u)

/* eoi_reg */

#define CSL_BOOTCFG_EOI_REG_EOI_VECTOR_MASK (0x000000FFu)
#define CSL_BOOTCFG_EOI_REG_EOI_VECTOR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EOI_REG_EOI_VECTOR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EOI_REG_RESETVAL     (0x00000000u)

/* fault_address_reg */

#define CSL_BOOTCFG_FAULT_ADDRESS_REG_FAULT_ADDR_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_FAULT_ADDRESS_REG_FAULT_ADDR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_FAULT_ADDRESS_REG_FAULT_ADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_ADDRESS_REG_RESETVAL (0x00000000u)

/* fault_status_reg */

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_ID_MASK (0x0F000000u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_ID_SHIFT (0x00000018u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_ID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_MSTID_MASK (0x00FF0000u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_MSTID_SHIFT (0x00000010u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_MSTID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_PRIVID_MASK (0x00001E00u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_PRIVID_SHIFT (0x00000009u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_PRIVID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_NS_MASK (0x00000080u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_NS_SHIFT (0x00000007u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_NS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_TYPE_MASK (0x0000003Fu)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_TYPE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_TYPE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_RESETVAL (0x00000000u)

/* fault_clear_reg */

#define CSL_BOOTCFG_FAULT_CLEAR_REG_FAULT_CLEAR_MASK (0x00000001u)
#define CSL_BOOTCFG_FAULT_CLEAR_REG_FAULT_CLEAR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_FAULT_CLEAR_REG_FAULT_CLEAR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_CLEAR_REG_RESETVAL (0x00000000u)

/* mac_id0 */

#define CSL_BOOTCFG_MAC_ID0_MAC_ID0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_MAC_ID0_MAC_ID0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MAC_ID0_MAC_ID0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MAC_ID0_RESETVAL     (0x00000000u)

/* mac_id1 */

#define CSL_BOOTCFG_MAC_ID1_MAC_ID1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_MAC_ID1_MAC_ID1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MAC_ID1_MAC_ID1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MAC_ID1_RESETVAL     (0x00000000u)

/* pcievendorid */

#define CSL_BOOTCFG_PCIEVENDORID_PCIEVENDORID_MASK (0x0000FFFFu)
#define CSL_BOOTCFG_PCIEVENDORID_PCIEVENDORID_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PCIEVENDORID_PCIEVENDORID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PCIEVENDORID_PCIEDEVICEID_MASK (0xFFFF0000u)
#define CSL_BOOTCFG_PCIEVENDORID_PCIEDEVICEID_SHIFT (0x00000010u)
#define CSL_BOOTCFG_PCIEVENDORID_PCIEDEVICEID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PCIEVENDORID_RESETVAL (0x00000000u)

/* disablestat */

#define CSL_BOOTCFG_DISABLESTAT_CGEMX_DIS_MASK (0x0000000Fu)
#define CSL_BOOTCFG_DISABLESTAT_CGEMX_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DISABLESTAT_CGEMX_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_A15X_DIS_MASK (0x00000300u)
#define CSL_BOOTCFG_DISABLESTAT_A15X_DIS_SHIFT (0x00000008u)
#define CSL_BOOTCFG_DISABLESTAT_A15X_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_TETRIS_DIS_MASK (0x00001000u)
#define CSL_BOOTCFG_DISABLESTAT_TETRIS_DIS_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_DISABLESTAT_TETRIS_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_CRYPTO_DIS_MASK (0x00002000u)
#define CSL_BOOTCFG_DISABLESTAT_CRYPTO_DIS_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_DISABLESTAT_CRYPTO_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_VCPABCD_DIS_MASK (0x00010000u)
#define CSL_BOOTCFG_DISABLESTAT_VCPABCD_DIS_SHIFT (0x00000010u)
#define CSL_BOOTCFG_DISABLESTAT_VCPABCD_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_RACA_TAC_DIS_MASK (0x00040000u)
#define CSL_BOOTCFG_DISABLESTAT_RACA_TAC_DIS_SHIFT (0x00000012u)
#define CSL_BOOTCFG_DISABLESTAT_RACA_TAC_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_TCPA_DIS_MASK (0x00100000u)
#define CSL_BOOTCFG_DISABLESTAT_TCPA_DIS_SHIFT (0x00000014u)
#define CSL_BOOTCFG_DISABLESTAT_TCPA_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_TCPB_DIS_MASK (0x00200000u)
#define CSL_BOOTCFG_DISABLESTAT_TCPB_DIS_SHIFT (0x00000015u)
#define CSL_BOOTCFG_DISABLESTAT_TCPB_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_FFTCA_DIS_MASK (0x00400000u)
#define CSL_BOOTCFG_DISABLESTAT_FFTCA_DIS_SHIFT (0x00000016u)
#define CSL_BOOTCFG_DISABLESTAT_FFTCA_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_FFTCB_DIS_MASK (0x00800000u)
#define CSL_BOOTCFG_DISABLESTAT_FFTCB_DIS_SHIFT (0x00000017u)
#define CSL_BOOTCFG_DISABLESTAT_FFTCB_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_BCP_DIS_MASK (0x02000000u)
#define CSL_BOOTCFG_DISABLESTAT_BCP_DIS_SHIFT (0x00000019u)
#define CSL_BOOTCFG_DISABLESTAT_BCP_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_IQN_AIL_DIS_MASK (0x04000000u)
#define CSL_BOOTCFG_DISABLESTAT_IQN_AIL_DIS_SHIFT (0x0000001Au)
#define CSL_BOOTCFG_DISABLESTAT_IQN_AIL_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_USB_DIS_MASK (0x08000000u)
#define CSL_BOOTCFG_DISABLESTAT_USB_DIS_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_DISABLESTAT_USB_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_DFE_DPD_DIS_MASK (0x10000000u)
#define CSL_BOOTCFG_DISABLESTAT_DFE_DPD_DIS_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_DISABLESTAT_DFE_DPD_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_DFE_DIS_MASK (0x20000000u)
#define CSL_BOOTCFG_DISABLESTAT_DFE_DIS_SHIFT (0x0000001Du)
#define CSL_BOOTCFG_DISABLESTAT_DFE_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_RESETVAL (0x00000000u)

/* lrstnmistat_clr */

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_0_CLR_MASK (0x00000001u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_0_CLR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_0_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_1_CLR_MASK (0x00000002u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_1_CLR_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_1_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_2_CLR_MASK (0x00000004u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_2_CLR_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_2_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_3_CLR_MASK (0x00000008u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_3_CLR_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_3_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_0_CLR_MASK (0x00000100u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_0_CLR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_0_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_1_CLR_MASK (0x00000200u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_1_CLR_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_1_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_2_CLR_MASK (0x00000400u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_2_CLR_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_2_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_3_CLR_MASK (0x00000800u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_3_CLR_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_3_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_RESETVAL (0x00000000u)

/* reset_stat_clr */

#define CSL_BOOTCFG_RESET_STAT_CLR_GRST_STAT_CLR_MASK (0x80000000u)
#define CSL_BOOTCFG_RESET_STAT_CLR_GRST_STAT_CLR_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_RESET_STAT_CLR_GRST_STAT_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_0_CLR_MASK (0x00000001u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_0_CLR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_0_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_1_CLR_MASK (0x00000002u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_1_CLR_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_1_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_2_CLR_MASK (0x00000004u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_2_CLR_SHIFT (0x00000002u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_2_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_3_CLR_MASK (0x00000008u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_3_CLR_SHIFT (0x00000003u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_3_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_RESETVAL (0x00000000u)

/* boot_complete */

#define CSL_BOOTCFG_BOOT_COMPLETE_ARM0_COMPLETE_MASK (0x00000100u)
#define CSL_BOOTCFG_BOOT_COMPLETE_ARM0_COMPLETE_SHIFT (0x00000008u)
#define CSL_BOOTCFG_BOOT_COMPLETE_ARM0_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_ARM1_COMPLETE_MASK (0x00000200u)
#define CSL_BOOTCFG_BOOT_COMPLETE_ARM1_COMPLETE_SHIFT (0x00000009u)
#define CSL_BOOTCFG_BOOT_COMPLETE_ARM1_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_GEM0_COMPLETE_MASK (0x00000001u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM0_COMPLETE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM0_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_GEM1_COMPLETE_MASK (0x00000002u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM1_COMPLETE_SHIFT (0x00000001u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM1_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_GEM2_COMPLETE_MASK (0x00000004u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM2_COMPLETE_SHIFT (0x00000002u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM2_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_GEM3_COMPLETE_MASK (0x00000008u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM3_COMPLETE_SHIFT (0x00000003u)
#define CSL_BOOTCFG_BOOT_COMPLETE_GEM3_COMPLETE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_COMPLETE_RESETVAL (0x00000000u)

/* boot_progress */

#define CSL_BOOTCFG_BOOT_PROGRESS_BOOT_PROGRESS_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_BOOT_PROGRESS_BOOT_PROGRESS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOT_PROGRESS_BOOT_PROGRESS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_PROGRESS_RESETVAL (0x00000000u)

/* reset_stat */

#define CSL_BOOTCFG_RESET_STAT_GRST_STAT_MASK (0x80000000u)
#define CSL_BOOTCFG_RESET_STAT_GRST_STAT_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_RESET_STAT_GRST_STAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT0_MASK (0x00000001u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT1_MASK (0x00000002u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT1_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT2_MASK (0x00000004u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT2_SHIFT (0x00000002u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT3_MASK (0x00000008u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT3_SHIFT (0x00000003u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_RESETVAL  (0x00000000u)

/* lrstnmistat */

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT0_MASK (0x00000001u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT1_MASK (0x00000002u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT1_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT2_MASK (0x00000004u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT2_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT3_MASK (0x00000008u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT3_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT0_MASK (0x00000100u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT0_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT1_MASK (0x00000200u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT1_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT2_MASK (0x00000400u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT2_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT3_MASK (0x00000800u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT3_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_RESETVAL (0x00000000u)

/* devcfg */

#define CSL_BOOTCFG_DEVCFG_SYSCLKOUTEN_MASK (0x00000001u)
#define CSL_BOOTCFG_DEVCFG_SYSCLKOUTEN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DEVCFG_SYSCLKOUTEN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVCFG_PCIESS_0_MODE_MASK (0x00000006u)
#define CSL_BOOTCFG_DEVCFG_PCIESS_0_MODE_SHIFT (0x00000001u)
#define CSL_BOOTCFG_DEVCFG_PCIESS_0_MODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVCFG_PCIESS_1_MODE_MASK (0x00000018u)
#define CSL_BOOTCFG_DEVCFG_PCIESS_1_MODE_SHIFT (0x00000003u)
#define CSL_BOOTCFG_DEVCFG_PCIESS_1_MODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVCFG_RESETVAL      (0x00000000u)

/* pwr_stat */

#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_MASK (0x00000002u)
#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_SHIFT (0x00000001u)
#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_MODE_MASK (0x00000004u)
#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_MODE_SHIFT (0x00000002u)
#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_MODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWR_STAT_PWR_STAT_GENERAL_MASK (0xFFFFFFF8u)
#define CSL_BOOTCFG_PWR_STAT_PWR_STAT_GENERAL_SHIFT (0x00000003u)
#define CSL_BOOTCFG_PWR_STAT_PWR_STAT_GENERAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWR_STAT_STANDBY_MASK (0x00000001u)
#define CSL_BOOTCFG_PWR_STAT_STANDBY_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWR_STAT_STANDBY_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWR_STAT_RESETVAL    (0x00000000u)

/* uart0_disable */

#define CSL_BOOTCFG_UART0_DISABLE_UART0_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_UART0_DISABLE_UART0_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_UART0_DISABLE_UART0_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_UART0_DISABLE_UART0_DIS_RSVD_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_UART0_DISABLE_UART0_DIS_RSVD_SHIFT (0x00000001u)
#define CSL_BOOTCFG_UART0_DISABLE_UART0_DIS_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_UART0_DISABLE_RESETVAL (0x00000000u)

/* uart1_disable */

#define CSL_BOOTCFG_UART1_DISABLE_UART1_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_UART1_DISABLE_UART1_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_UART1_DISABLE_UART1_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_UART1_DISABLE_UART1_DIS_RSVD_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_UART1_DISABLE_UART1_DIS_RSVD_SHIFT (0x00000001u)
#define CSL_BOOTCFG_UART1_DISABLE_UART1_DIS_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_UART1_DISABLE_RESETVAL (0x00000000u)

/* uart2_disable */

#define CSL_BOOTCFG_UART2_DISABLE_UART2_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_UART2_DISABLE_UART2_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_UART2_DISABLE_UART2_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_UART2_DISABLE_UART2_DIS_RSVD_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_UART2_DISABLE_UART2_DIS_RSVD_SHIFT (0x00000001u)
#define CSL_BOOTCFG_UART2_DISABLE_UART2_DIS_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_UART2_DISABLE_RESETVAL (0x00000000u)

/* uart3_disable */

#define CSL_BOOTCFG_UART3_DISABLE_UART3_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_UART3_DISABLE_UART3_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_UART3_DISABLE_UART3_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_UART3_DISABLE_UART3_DIS_RSVD_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_UART3_DISABLE_UART3_DIS_RSVD_SHIFT (0x00000001u)
#define CSL_BOOTCFG_UART3_DISABLE_UART3_DIS_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_UART3_DISABLE_RESETVAL (0x00000000u)

/* usb_disable */

#define CSL_BOOTCFG_USB_DISABLE_USB_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_USB_DISABLE_USB_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB_DISABLE_USB_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_DISABLE_USB_DIS_RSVD_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_USB_DISABLE_USB_DIS_RSVD_SHIFT (0x00000001u)
#define CSL_BOOTCFG_USB_DISABLE_USB_DIS_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_DISABLE_RESETVAL (0x00000000u)

/* sen0_0_efuse_reg0 */

#define CSL_BOOTCFG_SEN0_0_EFUSE_REG0_SEN0_0_EFUSE_REG0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN0_0_EFUSE_REG0_SEN0_0_EFUSE_REG0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN0_0_EFUSE_REG0_SEN0_0_EFUSE_REG0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN0_0_EFUSE_REG0_RESETVAL (0x00000000u)

/* sen1_0_efuse_reg1 */

#define CSL_BOOTCFG_SEN1_0_EFUSE_REG1_SEN1_0_EFUSE_REG1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN1_0_EFUSE_REG1_SEN1_0_EFUSE_REG1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN1_0_EFUSE_REG1_SEN1_0_EFUSE_REG1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN1_0_EFUSE_REG1_RESETVAL (0x00000000u)

/* sen2_0_efuse_reg2 */

#define CSL_BOOTCFG_SEN2_0_EFUSE_REG2_SEN2_0_EFUSE_REG2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN2_0_EFUSE_REG2_SEN2_0_EFUSE_REG2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN2_0_EFUSE_REG2_SEN2_0_EFUSE_REG2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN2_0_EFUSE_REG2_RESETVAL (0x00000000u)

/* sen3_0_efuse_reg3 */

#define CSL_BOOTCFG_SEN3_0_EFUSE_REG3_SEN3_0_EFUSE_REG3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN3_0_EFUSE_REG3_SEN3_0_EFUSE_REG3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN3_0_EFUSE_REG3_SEN3_0_EFUSE_REG3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN3_0_EFUSE_REG3_RESETVAL (0x00000000u)

/* sen0_1_efuse_reg4 */

#define CSL_BOOTCFG_SEN0_1_EFUSE_REG4_SEN0_1_EFUSE_REG4_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN0_1_EFUSE_REG4_SEN0_1_EFUSE_REG4_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN0_1_EFUSE_REG4_SEN0_1_EFUSE_REG4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN0_1_EFUSE_REG4_RESETVAL (0x00000000u)

/* sen1_1_efuse_reg5 */

#define CSL_BOOTCFG_SEN1_1_EFUSE_REG5_SEN1_1_EFUSE_REG5_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN1_1_EFUSE_REG5_SEN1_1_EFUSE_REG5_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN1_1_EFUSE_REG5_SEN1_1_EFUSE_REG5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN1_1_EFUSE_REG5_RESETVAL (0x00000000u)

/* sen2_1_efuse_reg6 */

#define CSL_BOOTCFG_SEN2_1_EFUSE_REG6_SEN2_1_EFUSE_REG6_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN2_1_EFUSE_REG6_SEN2_1_EFUSE_REG6_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN2_1_EFUSE_REG6_SEN2_1_EFUSE_REG6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN2_1_EFUSE_REG6_RESETVAL (0x00000000u)

/* sen3_1_efuse_reg7 */

#define CSL_BOOTCFG_SEN3_1_EFUSE_REG7_SEN3_1_EFUSE_REG7_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN3_1_EFUSE_REG7_SEN3_1_EFUSE_REG7_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN3_1_EFUSE_REG7_SEN3_1_EFUSE_REG7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN3_1_EFUSE_REG7_RESETVAL (0x00000000u)

/* sen0_2_efuse_reg8 */

#define CSL_BOOTCFG_SEN0_2_EFUSE_REG8_SEN0_2_EFUSE_REG8_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN0_2_EFUSE_REG8_SEN0_2_EFUSE_REG8_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN0_2_EFUSE_REG8_SEN0_2_EFUSE_REG8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN0_2_EFUSE_REG8_RESETVAL (0x00000000u)

/* sen1_2_efuse_reg9 */

#define CSL_BOOTCFG_SEN1_2_EFUSE_REG9_SEN1_2_EFUSE_REG9_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN1_2_EFUSE_REG9_SEN1_2_EFUSE_REG9_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN1_2_EFUSE_REG9_SEN1_2_EFUSE_REG9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN1_2_EFUSE_REG9_RESETVAL (0x00000000u)

/* sen2_2_efuse_reg10 */

#define CSL_BOOTCFG_SEN2_2_EFUSE_REG10_SEN2_2_EFUSE_REG10_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN2_2_EFUSE_REG10_SEN2_2_EFUSE_REG10_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN2_2_EFUSE_REG10_SEN2_2_EFUSE_REG10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN2_2_EFUSE_REG10_RESETVAL (0x00000000u)

/* sen3_2_efuse_reg11 */

#define CSL_BOOTCFG_SEN3_2_EFUSE_REG11_SEN3_2_EFUSE_REG11_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN3_2_EFUSE_REG11_SEN3_2_EFUSE_REG11_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN3_2_EFUSE_REG11_SEN3_2_EFUSE_REG11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN3_2_EFUSE_REG11_RESETVAL (0x00000000u)

/* sen0_3_efuse_reg12 */

#define CSL_BOOTCFG_SEN0_3_EFUSE_REG12_SEN0_3_EFUSE_REG12_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN0_3_EFUSE_REG12_SEN0_3_EFUSE_REG12_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN0_3_EFUSE_REG12_SEN0_3_EFUSE_REG12_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN0_3_EFUSE_REG12_RESETVAL (0x00000000u)

/* sen1_3_efuse_reg13 */

#define CSL_BOOTCFG_SEN1_3_EFUSE_REG13_SEN1_3_EFUSE_REG13_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN1_3_EFUSE_REG13_SEN1_3_EFUSE_REG13_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN1_3_EFUSE_REG13_SEN1_3_EFUSE_REG13_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN1_3_EFUSE_REG13_RESETVAL (0x00000000u)

/* sen2_3_efuse_reg14 */

#define CSL_BOOTCFG_SEN2_3_EFUSE_REG14_SEN2_3_EFUSE_REG14_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN2_3_EFUSE_REG14_SEN2_3_EFUSE_REG14_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN2_3_EFUSE_REG14_SEN2_3_EFUSE_REG14_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN2_3_EFUSE_REG14_RESETVAL (0x00000000u)

/* sen3_3_efuse_reg15 */

#define CSL_BOOTCFG_SEN3_3_EFUSE_REG15_SEN3_3_EFUSE_REG15_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN3_3_EFUSE_REG15_SEN3_3_EFUSE_REG15_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN3_3_EFUSE_REG15_SEN3_3_EFUSE_REG15_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN3_3_EFUSE_REG15_RESETVAL (0x00000000u)

/* nmigr_0 */

#define CSL_BOOTCFG_NMIGR_0_NMIGR_0_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_0_NMIGR_0_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_0_NMIGR_0_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_0_RESETVAL     (0x00000000u)

/* nmigr_1 */

#define CSL_BOOTCFG_NMIGR_1_NMIGR_1_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_1_NMIGR_1_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_1_NMIGR_1_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_1_RESETVAL     (0x00000000u)

/* nmigr_2 */

#define CSL_BOOTCFG_NMIGR_2_NMIGR_2_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_2_NMIGR_2_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_2_NMIGR_2_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_2_RESETVAL     (0x00000000u)

/* nmigr_3 */

#define CSL_BOOTCFG_NMIGR_3_NMIGR_3_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_3_NMIGR_3_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_3_NMIGR_3_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_3_RESETVAL     (0x00000000u)

/* ipcgr0 */

#define CSL_BOOTCFG_IPCGR0_IPCGR0_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR0_IPCGR0_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR0_IPCGR0_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGR0_IPCGR0_SRC_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCGR0_IPCGR0_SRC_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCGR0_IPCGR0_SRC_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGR0_RESETVAL      (0x00000000u)

/* ipcgr1 */

#define CSL_BOOTCFG_IPCGR1_IPCGR1_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR1_IPCGR1_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR1_IPCGR1_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGR1_IPCGR1_SRC_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCGR1_IPCGR1_SRC_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCGR1_IPCGR1_SRC_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGR1_RESETVAL      (0x00000000u)

/* ipcgr2 */

#define CSL_BOOTCFG_IPCGR2_IPCGR2_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR2_IPCGR2_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR2_IPCGR2_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGR2_IPCGR2_SRC_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCGR2_IPCGR2_SRC_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCGR2_IPCGR2_SRC_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGR2_RESETVAL      (0x00000000u)

/* ipcgr3 */

#define CSL_BOOTCFG_IPCGR3_IPCGR3_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR3_IPCGR3_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR3_IPCGR3_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGR3_IPCGR3_SRC_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCGR3_IPCGR3_SRC_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCGR3_IPCGR3_SRC_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGR3_RESETVAL      (0x00000000u)

/* ipcgr8 */

#define CSL_BOOTCFG_IPCGR8_IPCGR8_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR8_IPCGR8_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR8_IPCGR8_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGR8_IPCGR8_SRC_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCGR8_IPCGR8_SRC_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCGR8_IPCGR8_SRC_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGR8_RESETVAL      (0x00000000u)

/* ipcgr9 */

#define CSL_BOOTCFG_IPCGR9_IPCGR9_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR9_IPCGR9_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR9_IPCGR9_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGR9_IPCGR9_SRC_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCGR9_IPCGR9_SRC_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCGR9_IPCGR9_SRC_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGR9_RESETVAL      (0x00000000u)

/* ipcgrh */

#define CSL_BOOTCFG_IPCGRH_IPCGRH_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGRH_IPCGRH_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGRH_IPCGRH_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGRH_IPCGRH_SRC_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCGRH_IPCGRH_SRC_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCGRH_IPCGRH_SRC_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCGRH_RESETVAL      (0x00000000u)

/* ipcar0 */

#define CSL_BOOTCFG_IPCAR0_IPCGR0_SRC_CLR_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCAR0_IPCGR0_SRC_CLR_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCAR0_IPCGR0_SRC_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCAR0_RESETVAL      (0x00000000u)

/* ipcar1 */

#define CSL_BOOTCFG_IPCAR1_IPCGR1_SRC_CLR_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCAR1_IPCGR1_SRC_CLR_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCAR1_IPCGR1_SRC_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCAR1_RESETVAL      (0x00000000u)

/* ipcar2 */

#define CSL_BOOTCFG_IPCAR2_IPCGR2_SRC_CLR_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCAR2_IPCGR2_SRC_CLR_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCAR2_IPCGR2_SRC_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCAR2_RESETVAL      (0x00000000u)

/* ipcar3 */

#define CSL_BOOTCFG_IPCAR3_IPCGR3_SRC_CLR_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCAR3_IPCGR3_SRC_CLR_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCAR3_IPCGR3_SRC_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCAR3_RESETVAL      (0x00000000u)

/* ipcar8 */

#define CSL_BOOTCFG_IPCAR8_IPCGR8_SRC_CLR_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCAR8_IPCGR8_SRC_CLR_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCAR8_IPCGR8_SRC_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCAR8_RESETVAL      (0x00000000u)

/* ipcar9 */

#define CSL_BOOTCFG_IPCAR9_IPCGR9_SRC_CLR_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCAR9_IPCGR9_SRC_CLR_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCAR9_IPCGR9_SRC_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCAR9_RESETVAL      (0x00000000u)

/* ipcarh */

#define CSL_BOOTCFG_IPCARH_IPCGRH_SRC_CLR_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCARH_IPCGRH_SRC_CLR_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCARH_IPCGRH_SRC_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IPCARH_RESETVAL      (0x00000000u)

/* tinpsel0 */

#define CSL_BOOTCFG_TINPSEL0_TINPLSEL0_MASK (0x00000007u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEL0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL0_TINPLSEH0_MASK (0x00000070u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEH0_SHIFT (0x00000004u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEH0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL0_TINPLSEL1_MASK (0x00000700u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEL1_SHIFT (0x00000008u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEL1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL0_TINPLSEH1_MASK (0x00007000u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEH1_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEH1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL0_TINPLSEL2_MASK (0x00070000u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEL2_SHIFT (0x00000010u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEL2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL0_TINPLSEH2_MASK (0x00700000u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEH2_SHIFT (0x00000014u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEH2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL0_TINPLSEL3_MASK (0x07000000u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEL3_SHIFT (0x00000018u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEL3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL0_TINPLSEH3_MASK (0x70000000u)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEH3_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_TINPSEL0_TINPLSEH3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL0_RESETVAL    (0x00000000u)

/* tinpsel2 */

#define CSL_BOOTCFG_TINPSEL2_TINPLSEL8_MASK (0x00000007u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEL8_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEL8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL2_TINPLSEH8_MASK (0x00000070u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEH8_SHIFT (0x00000004u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEH8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL2_TINPLSEL9_MASK (0x00000700u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEL9_SHIFT (0x00000008u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEL9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL2_TINPLSEH9_MASK (0x00007000u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEH9_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEH9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL2_TINPLSEL10_MASK (0x00070000u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEL10_SHIFT (0x00000010u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEL10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL2_TINPLSEH10_MASK (0x00700000u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEH10_SHIFT (0x00000014u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEH10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL2_TINPLSEL11_MASK (0x07000000u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEL11_SHIFT (0x00000018u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEL11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL2_TINPLSEH11_MASK (0x70000000u)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEH11_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_TINPSEL2_TINPLSEH11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL2_RESETVAL    (0x00000000u)

/* tinpsel3 */

#define CSL_BOOTCFG_TINPSEL3_TINPLSEL12_MASK (0x00000007u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEL12_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEL12_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL3_TINPLSEH12_MASK (0x00000070u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEH12_SHIFT (0x00000004u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEH12_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL3_TINPLSEL13_MASK (0x00000700u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEL13_SHIFT (0x00000008u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEL13_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL3_TINPLSEH13_MASK (0x00007000u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEH13_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEH13_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL3_TINPLSEL14_MASK (0x00070000u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEL14_SHIFT (0x00000010u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEL14_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL3_TINPLSEH14_MASK (0x00700000u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEH14_SHIFT (0x00000014u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEH14_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL3_TINPLSEL15_MASK (0x07000000u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEL15_SHIFT (0x00000018u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEL15_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL3_TINPLSEH15_MASK (0x70000000u)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEH15_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_TINPSEL3_TINPLSEH15_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL3_RESETVAL    (0x00000000u)

/* tinpsel4 */

#define CSL_BOOTCFG_TINPSEL4_TINPLSEL16_MASK (0x00000007u)
#define CSL_BOOTCFG_TINPSEL4_TINPLSEL16_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TINPSEL4_TINPLSEL16_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL4_TINPLSEH16_MASK (0x00000070u)
#define CSL_BOOTCFG_TINPSEL4_TINPLSEH16_SHIFT (0x00000004u)
#define CSL_BOOTCFG_TINPSEL4_TINPLSEH16_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL4_TINPLSEL17_MASK (0x00000700u)
#define CSL_BOOTCFG_TINPSEL4_TINPLSEL17_SHIFT (0x00000008u)
#define CSL_BOOTCFG_TINPSEL4_TINPLSEL17_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL4_TINPLSEH17_MASK (0x00007000u)
#define CSL_BOOTCFG_TINPSEL4_TINPLSEH17_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_TINPSEL4_TINPLSEH17_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TINPSEL4_RESETVAL    (0x00000000u)

/* toutpsel0 */

#define CSL_BOOTCFG_TOUTPSEL0_TOUTPSEL0_MASK (0x0000003Fu)
#define CSL_BOOTCFG_TOUTPSEL0_TOUTPSEL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TOUTPSEL0_TOUTPSEL0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TOUTPSEL0_TOUTPSEL1_MASK (0x00003F00u)
#define CSL_BOOTCFG_TOUTPSEL0_TOUTPSEL1_SHIFT (0x00000008u)
#define CSL_BOOTCFG_TOUTPSEL0_TOUTPSEL1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TOUTPSEL0_TOUTPSEL2_MASK (0x003F0000u)
#define CSL_BOOTCFG_TOUTPSEL0_TOUTPSEL2_SHIFT (0x00000010u)
#define CSL_BOOTCFG_TOUTPSEL0_TOUTPSEL2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TOUTPSEL0_TOUTPSEL3_MASK (0x3F000000u)
#define CSL_BOOTCFG_TOUTPSEL0_TOUTPSEL3_SHIFT (0x00000018u)
#define CSL_BOOTCFG_TOUTPSEL0_TOUTPSEL3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TOUTPSEL0_RESETVAL   (0x00000000u)

/* toutpsel1 */

#define CSL_BOOTCFG_TOUTPSEL1_TOUTPSEL4_MASK (0x0000003Fu)
#define CSL_BOOTCFG_TOUTPSEL1_TOUTPSEL4_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TOUTPSEL1_TOUTPSEL4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TOUTPSEL1_TOUTPSEL5_MASK (0x00003F00u)
#define CSL_BOOTCFG_TOUTPSEL1_TOUTPSEL5_SHIFT (0x00000008u)
#define CSL_BOOTCFG_TOUTPSEL1_TOUTPSEL5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TOUTPSEL1_TOUTPSEL6_MASK (0x003F0000u)
#define CSL_BOOTCFG_TOUTPSEL1_TOUTPSEL6_SHIFT (0x00000010u)
#define CSL_BOOTCFG_TOUTPSEL1_TOUTPSEL6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TOUTPSEL1_TOUTPSEL7_MASK (0x3F000000u)
#define CSL_BOOTCFG_TOUTPSEL1_TOUTPSEL7_SHIFT (0x00000018u)
#define CSL_BOOTCFG_TOUTPSEL1_TOUTPSEL7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TOUTPSEL1_RESETVAL   (0x00000000u)

#define CSL_BOOTCFG_USB_EBC_IN_CTL_EBC15_SEL_MASK (0x00000003u)
#define CSL_BOOTCFG_USB_EBC_IN_CTL_EBC15_SEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB_EBC_IN_CTL_EBC15_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_EBC_IN_CTL_EBC14_SEL_MASK (0x00000030u)
#define CSL_BOOTCFG_USB_EBC_IN_CTL_EBC14_SEL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB_EBC_IN_CTL_EBC14_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB_EBC_IN_CTL_RESETVAL (0x00000000u)

/* rstmux0 */

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_DELAY0_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_DELAY0_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_DELAY0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT0_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT0_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT_CLR0_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT_CLR0_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT_CLR0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_LOCK0_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_LOCK0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_LOCK0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_OMODE0_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_OMODE0_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_OMODE0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RESETVAL     (0x00000000u)

/* rstmux1 */

#define CSL_BOOTCFG_RSTMUX1_RSTMUX_DELAY1_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_DELAY1_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_DELAY1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX1_RSTMUX_EVSTAT1_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_EVSTAT1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_EVSTAT1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX1_RSTMUX_EVSTAT_CLR1_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_EVSTAT_CLR1_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_EVSTAT_CLR1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX1_RSTMUX_LOCK1_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_LOCK1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_LOCK1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX1_RSTMUX_OMODE1_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_OMODE1_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX1_RSTMUX_OMODE1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX1_RESETVAL     (0x00000000u)

/* rstmux2 */

#define CSL_BOOTCFG_RSTMUX2_RSTMUX_DELAY2_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_DELAY2_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_DELAY2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX2_RSTMUX_EVSTAT2_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_EVSTAT2_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_EVSTAT2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX2_RSTMUX_EVSTAT_CLR2_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_EVSTAT_CLR2_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_EVSTAT_CLR2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX2_RSTMUX_LOCK2_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_LOCK2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_LOCK2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX2_RSTMUX_OMODE2_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_OMODE2_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX2_RSTMUX_OMODE2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX2_RESETVAL     (0x00000000u)

/* rstmux3 */

#define CSL_BOOTCFG_RSTMUX3_RSTMUX_DELAY3_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_DELAY3_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_DELAY3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX3_RSTMUX_EVSTAT3_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_EVSTAT3_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_EVSTAT3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX3_RSTMUX_EVSTAT_CLR3_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_EVSTAT_CLR3_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_EVSTAT_CLR3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX3_RSTMUX_LOCK3_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_LOCK3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_LOCK3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX3_RSTMUX_OMODE3_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_OMODE3_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX3_RSTMUX_OMODE3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX3_RESETVAL     (0x00000000u)

/* rstmux8 */

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_DELAY8_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_DELAY8_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_DELAY8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT8_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT8_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT_CLR8_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT_CLR8_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT_CLR8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_LOCK8_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_LOCK8_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_LOCK8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_OMODE8_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_OMODE8_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_OMODE8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RESETVAL     (0x00000000u)

/* rstmux9 */

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_DELAY9_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_DELAY9_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_DELAY9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT9_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT9_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT_CLR9_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT_CLR9_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT_CLR9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_LOCK9_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_LOCK9_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_LOCK9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_OMODE9_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_OMODE9_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_OMODE9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RESETVAL     (0x00000000u)

/* main_pll_ctl0 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_MASK                     (0x0000003FU)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_SHIFT                    (0U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_RESETVAL                 (0x00000000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_MAX                      (0x0000003fU)

#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_MASK                     (0x0007F000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_SHIFT                    (12U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_RESETVAL                 (0x00000000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_MAX                      (0x0000007fU)

#define CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_MASK                    (0xFF000000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_SHIFT                   (24U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_RESETVAL                (0x00000005U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_MAX                     (0x000000ffU)
#endif

#define CSL_BOOTCFG_MAIN_PLL_CTL0_CORE_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_CORE_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_CORE_PLL_CTL0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MAIN_PLL_CTL0_RESETVAL (0x00000000u)

/* main_pll_ctl1 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_MASK                    (0x0000000FU)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_SHIFT                   (0U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_RESETVAL                (0x00000000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_MAX                     (0x0000000fU)

#define CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_MASK                    (0x00000040U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_SHIFT                   (6U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_MAX                     (0x00000001U)
#endif

#define CSL_BOOTCFG_MAIN_PLL_CTL1_CORE_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_CORE_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_CORE_PLL_CTL1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MAIN_PLL_CTL1_RESETVAL (0x00000000u)

/* pass_pll_ctl0 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLD_MASK                     (0x0000003FU)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLD_SHIFT                    (0U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLD_RESETVAL                 (0x00000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLD_MAX                      (0x0000003fU)

#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_MASK                     (0x0007FFC0U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_SHIFT                    (6U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_RESETVAL                 (0x00000013U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_MAX                      (0x00001fffU)

#define CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_MASK                    (0x00780000U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_SHIFT                   (19U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_MAX                     (0x0000000fU)

#define CSL_BOOTCFG_PASS_PLL_CTL0_BYPASS_MASK                    (0x00800000U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BYPASS_SHIFT                   (23U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BYPASS_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BYPASS_MAX                     (0x00000001U)

#define CSL_BOOTCFG_PASS_PLL_CTL0_BWADJ_MASK                     (0xFF000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BWADJ_SHIFT                    (24U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BWADJ_RESETVAL                 (0x00000009U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BWADJ_MAX                      (0x000000ffU)
#endif

#define CSL_BOOTCFG_PASS_PLL_CTL0_PA_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PA_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PA_PLL_CTL0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PASS_PLL_CTL0_RESETVAL (0x00000000u)

/* pass_pll_ctl1 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_PASS_PLL_CTL1_BWADJ_MASK                    (0x0000000FU)
#define CSL_BOOTCFG_PASS_PLL_CTL1_BWADJ_SHIFT                   (0U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_BWADJ_RESETVAL                (0x00000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_BWADJ_MAX                     (0x0000000fU)

#define CSL_BOOTCFG_PASS_PLL_CTL1_ENSAT_MASK                    (0x00000040U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_ENSAT_SHIFT                   (6U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_ENSAT_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_ENSAT_MAX                     (0x00000001U)

#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_MASK                   (0x00002000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_SHIFT                  (13U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_RESETVAL               (0x00000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_MAX                    (0x00000001U)

#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_MASK                   (0x00004000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_SHIFT                  (14U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_RESETVAL               (0x00000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_MAX                    (0x00000001U)
#endif

#define CSL_BOOTCFG_PASS_PLL_CTL1_PA_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PA_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PA_PLL_CTL1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PASS_PLL_CTL1_RESETVAL (0x00000000u)

/* ddra_pll_ctl0 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLD_MASK                    (0x0000003FU)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLD_SHIFT                   (0U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLD_RESETVAL                (0x00000000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLD_MAX                     (0x0000003fU)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLM_MASK                    (0x0007FFC0U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLM_SHIFT                   (6U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLM_RESETVAL                (0x00000013U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLM_MAX                     (0x00001fffU)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_CLKOD_MASK                   (0x00780000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_CLKOD_SHIFT                  (19U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_CLKOD_RESETVAL               (0x00000001U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_CLKOD_MAX                    (0x0000000fU)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BYPASS_MASK                  (0x00800000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BYPASS_SHIFT                 (23U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BYPASS_RESETVAL              (0x00000001U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BYPASS_MAX                   (0x00000001U)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BWADJ_MASK                   (0xFF000000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BWADJ_SHIFT                  (24U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BWADJ_RESETVAL               (0x00000009U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BWADJ_MAX                    (0x000000ffU)
#endif

#define CSL_BOOTCFG_DDRA_PLL_CTL0_DDRA_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DDRA_PLL_CTL0_DDRA_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DDRA_PLL_CTL0_DDRA_PLL_CTL0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DDRA_PLL_CTL0_RESETVAL (0x00000000u)

/* ddra_pll_ctl1 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_BWADJ_MASK                   (0x0000000FU)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_BWADJ_SHIFT                  (0U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_BWADJ_RESETVAL               (0x00000000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_BWADJ_MAX                    (0x0000000fU)

#define CSL_BOOTCFG_DDR3A_PLL_CTL1_ENSAT_MASK                   (0x00000040U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_ENSAT_SHIFT                  (6U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_ENSAT_RESETVAL               (0x00000001U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_ENSAT_MAX                    (0x00000001U)

#define CSL_BOOTCFG_DDR3A_PLL_CTL1_PLLRST_MASK                  (0x00004000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_PLLRST_SHIFT                 (14U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_PLLRST_RESETVAL              (0x00000000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_PLLRST_MAX                   (0x00000001U)
#endif

#define CSL_BOOTCFG_DDRA_PLL_CTL1_DDRA_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DDRA_PLL_CTL1_DDRA_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DDRA_PLL_CTL1_DDRA_PLL_CTL1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DDRA_PLL_CTL1_RESETVAL (0x00000000u)

/* arm_pll_ctl0 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLD_MASK                      (0x0000003FU)
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLD_SHIFT                     (0U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLD_RESETVAL                  (0x00000000U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLD_MAX                       (0x0000003fU)

#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLM_MASK                      (0x0007FFC0U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLM_SHIFT                     (6U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLM_RESETVAL                  (0x00000013U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_PLLM_MAX                       (0x00001fffU)

#define CSL_BOOTCFG_ARM_PLL_CTL0_CLKOD_MASK                     (0x00780000U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_CLKOD_SHIFT                    (19U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_CLKOD_RESETVAL                 (0x00000001U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_CLKOD_MAX                      (0x0000000fU)

#define CSL_BOOTCFG_ARM_PLL_CTL0_BYPASS_MASK                    (0x00800000U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_BYPASS_SHIFT                   (23U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_BYPASS_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_BYPASS_MAX                     (0x00000001U)

#define CSL_BOOTCFG_ARM_PLL_CTL0_BWADJ_MASK                     (0xFF000000U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_BWADJ_SHIFT                    (24U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_BWADJ_RESETVAL                 (0x00000009U)
#define CSL_BOOTCFG_ARM_PLL_CTL0_BWADJ_MAX                      (0x000000ffU)
#endif

#define CSL_BOOTCFG_ARM_PLL_CTL0_ARM_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARM_PLL_CTL0_ARM_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_PLL_CTL0_ARM_PLL_CTL0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARM_PLL_CTL0_RESETVAL (0x00000000u)

/* arm_pll_ctl1 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_ARM_PLL_CTL1_BWADJ_MASK                     (0x0000000FU)
#define CSL_BOOTCFG_ARM_PLL_CTL1_BWADJ_SHIFT                    (0U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_BWADJ_RESETVAL                 (0x00000000U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_BWADJ_MAX                      (0x0000000fU)

#define CSL_BOOTCFG_ARM_PLL_CTL1_ENSAT_MASK                     (0x00000040U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_ENSAT_SHIFT                    (6U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_ENSAT_RESETVAL                 (0x00000001U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_ENSAT_MAX                      (0x00000001U)

#define CSL_BOOTCFG_ARM_PLL_CTL1_PLLRST_MASK                    (0x00004000U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_PLLRST_SHIFT                   (14U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_PLLRST_RESETVAL                (0x00000000U)
#define CSL_BOOTCFG_ARM_PLL_CTL1_PLLRST_MAX
#endif

#define CSL_BOOTCFG_ARM_PLL_CTL1_ARM_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARM_PLL_CTL1_ARM_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_PLL_CTL1_ARM_PLL_CTL1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARM_PLL_CTL1_RESETVAL (0x00000000u)

/* dfe_pll_ctl0 */

#define CSL_BOOTCFG_DFE_PLL_CTL0_DFE_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DFE_PLL_CTL0_DFE_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DFE_PLL_CTL0_DFE_PLL_CTL0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFE_PLL_CTL0_RESETVAL (0x00000000u)

/* dfe_pll_ctl1 */

#define CSL_BOOTCFG_DFE_PLL_CTL1_DFE_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DFE_PLL_CTL1_DFE_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DFE_PLL_CTL1_DFE_PLL_CTL1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFE_PLL_CTL1_RESETVAL (0x00000000u)

/* secure_control */

#define CSL_BOOTCFG_SECURE_CONTROL_PBIST_SECURE_EN_MASK (0x00000001u)
#define CSL_BOOTCFG_SECURE_CONTROL_PBIST_SECURE_EN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SECURE_CONTROL_PBIST_SECURE_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SECURE_CONTROL_VUSR_SEC_EN_MASK (0x00000002u)
#define CSL_BOOTCFG_SECURE_CONTROL_VUSR_SEC_EN_SHIFT (0x00000001u)
#define CSL_BOOTCFG_SECURE_CONTROL_VUSR_SEC_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SECURE_CONTROL_RESETVAL (0x00000000u)

/* armendian_cfg0_0 */

#define CSL_BOOTCFG_ARMENDIAN_CFG0_0_ARMENDIAN_CFG0_BASEADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARMENDIAN_CFG0_0_ARMENDIAN_CFG0_BASEADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARMENDIAN_CFG0_0_ARMENDIAN_CFG0_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG0_0_ARMENDIAN_CFG0_RSVD0_MASK (0x000000FFu)
#define CSL_BOOTCFG_ARMENDIAN_CFG0_0_ARMENDIAN_CFG0_RSVD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG0_0_ARMENDIAN_CFG0_RSVD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG0_0_RESETVAL (0x00000000u)

/* armendian_cfg0_1 */

#define CSL_BOOTCFG_ARMENDIAN_CFG0_1_ARMENDIAN_CFG0_BASEADDR_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARMENDIAN_CFG0_1_ARMENDIAN_CFG0_BASEADDR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG0_1_ARMENDIAN_CFG0_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG0_1_ARMENDIAN_CFG0_RSVD1_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_ARMENDIAN_CFG0_1_ARMENDIAN_CFG0_RSVD1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_ARMENDIAN_CFG0_1_ARMENDIAN_CFG0_RSVD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG0_1_RESETVAL (0x00000000u)

/* armendian_cfg0_2 */

#define CSL_BOOTCFG_ARMENDIAN_CFG0_2_ARMENDIAN_CFG0_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG0_2_ARMENDIAN_CFG0_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG0_2_ARMENDIAN_CFG0_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG0_2_ARMENDIAN_CFG0_RSVD2_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_ARMENDIAN_CFG0_2_ARMENDIAN_CFG0_RSVD2_SHIFT (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG0_2_ARMENDIAN_CFG0_RSVD2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG0_2_RESETVAL (0x00000000u)

/* armendian_cfg1_0 */

#define CSL_BOOTCFG_ARMENDIAN_CFG1_0_ARMENDIAN_CFG1_BASEADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARMENDIAN_CFG1_0_ARMENDIAN_CFG1_BASEADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARMENDIAN_CFG1_0_ARMENDIAN_CFG1_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG1_0_ARMENDIAN_CFG1_RSVD0_MASK (0x000000FFu)
#define CSL_BOOTCFG_ARMENDIAN_CFG1_0_ARMENDIAN_CFG1_RSVD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG1_0_ARMENDIAN_CFG1_RSVD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG1_0_RESETVAL (0x00000000u)

/* armendian_cfg1_1 */

#define CSL_BOOTCFG_ARMENDIAN_CFG1_1_ARMENDIAN_CFG1_BASEADDR_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARMENDIAN_CFG1_1_ARMENDIAN_CFG1_BASEADDR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG1_1_ARMENDIAN_CFG1_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG1_1_ARMENDIAN_CFG1_RSVD1_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_ARMENDIAN_CFG1_1_ARMENDIAN_CFG1_RSVD1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_ARMENDIAN_CFG1_1_ARMENDIAN_CFG1_RSVD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG1_1_RESETVAL (0x00000000u)

/* armendian_cfg1_2 */

#define CSL_BOOTCFG_ARMENDIAN_CFG1_2_ARMENDIAN_CFG1_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG1_2_ARMENDIAN_CFG1_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG1_2_ARMENDIAN_CFG1_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG1_2_ARMENDIAN_CFG1_RSVD2_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_ARMENDIAN_CFG1_2_ARMENDIAN_CFG1_RSVD2_SHIFT (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG1_2_ARMENDIAN_CFG1_RSVD2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG1_2_RESETVAL (0x00000000u)

/* armendian_cfg2_0 */

#define CSL_BOOTCFG_ARMENDIAN_CFG2_0_ARMENDIAN_CFG2_BASEADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARMENDIAN_CFG2_0_ARMENDIAN_CFG2_BASEADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARMENDIAN_CFG2_0_ARMENDIAN_CFG2_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG2_0_ARMENDIAN_CFG2_RSVD0_MASK (0x000000FFu)
#define CSL_BOOTCFG_ARMENDIAN_CFG2_0_ARMENDIAN_CFG2_RSVD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG2_0_ARMENDIAN_CFG2_RSVD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG2_0_RESETVAL (0x00000000u)

/* armendian_cfg2_1 */

#define CSL_BOOTCFG_ARMENDIAN_CFG2_1_ARMENDIAN_CFG2_BASEADDR_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARMENDIAN_CFG2_1_ARMENDIAN_CFG2_BASEADDR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG2_1_ARMENDIAN_CFG2_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG2_1_ARMENDIAN_CFG2_RSVD1_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_ARMENDIAN_CFG2_1_ARMENDIAN_CFG2_RSVD1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_ARMENDIAN_CFG2_1_ARMENDIAN_CFG2_RSVD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG2_1_RESETVAL (0x00000000u)

/* armendian_cfg2_2 */

#define CSL_BOOTCFG_ARMENDIAN_CFG2_2_ARMENDIAN_CFG2_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG2_2_ARMENDIAN_CFG2_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG2_2_ARMENDIAN_CFG2_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG2_2_ARMENDIAN_CFG2_RSVD2_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_ARMENDIAN_CFG2_2_ARMENDIAN_CFG2_RSVD2_SHIFT (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG2_2_ARMENDIAN_CFG2_RSVD2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG2_2_RESETVAL (0x00000000u)

/* armendian_cfg3_0 */

#define CSL_BOOTCFG_ARMENDIAN_CFG3_0_ARMENDIAN_CFG3_BASEADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARMENDIAN_CFG3_0_ARMENDIAN_CFG3_BASEADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARMENDIAN_CFG3_0_ARMENDIAN_CFG3_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG3_0_ARMENDIAN_CFG3_RSVD0_MASK (0x000000FFu)
#define CSL_BOOTCFG_ARMENDIAN_CFG3_0_ARMENDIAN_CFG3_RSVD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG3_0_ARMENDIAN_CFG3_RSVD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG3_0_RESETVAL (0x00000000u)

/* armendian_cfg3_1 */

#define CSL_BOOTCFG_ARMENDIAN_CFG3_1_ARMENDIAN_CFG3_BASEADDR_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARMENDIAN_CFG3_1_ARMENDIAN_CFG3_BASEADDR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG3_1_ARMENDIAN_CFG3_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG3_1_ARMENDIAN_CFG3_RSVD1_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_ARMENDIAN_CFG3_1_ARMENDIAN_CFG3_RSVD1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_ARMENDIAN_CFG3_1_ARMENDIAN_CFG3_RSVD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG3_1_RESETVAL (0x00000000u)

/* armendian_cfg3_2 */

#define CSL_BOOTCFG_ARMENDIAN_CFG3_2_ARMENDIAN_CFG3_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG3_2_ARMENDIAN_CFG3_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG3_2_ARMENDIAN_CFG3_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG3_2_ARMENDIAN_CFG3_RSVD2_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_ARMENDIAN_CFG3_2_ARMENDIAN_CFG3_RSVD2_SHIFT (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG3_2_ARMENDIAN_CFG3_RSVD2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG3_2_RESETVAL (0x00000000u)

/* armendian_cfg4_0 */

#define CSL_BOOTCFG_ARMENDIAN_CFG4_0_ARMENDIAN_CFG4_BASEADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARMENDIAN_CFG4_0_ARMENDIAN_CFG4_BASEADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARMENDIAN_CFG4_0_ARMENDIAN_CFG4_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG4_0_ARMENDIAN_CFG4_RSVD0_MASK (0x000000FFu)
#define CSL_BOOTCFG_ARMENDIAN_CFG4_0_ARMENDIAN_CFG4_RSVD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG4_0_ARMENDIAN_CFG4_RSVD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG4_0_RESETVAL (0x00000000u)

/* armendian_cfg4_1 */

#define CSL_BOOTCFG_ARMENDIAN_CFG4_1_ARMENDIAN_CFG4_BASEADDR_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARMENDIAN_CFG4_1_ARMENDIAN_CFG4_BASEADDR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG4_1_ARMENDIAN_CFG4_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG4_1_ARMENDIAN_CFG4_RSVD1_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_ARMENDIAN_CFG4_1_ARMENDIAN_CFG4_RSVD1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_ARMENDIAN_CFG4_1_ARMENDIAN_CFG4_RSVD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG4_1_RESETVAL (0x00000000u)

/* armendian_cfg4_2 */

#define CSL_BOOTCFG_ARMENDIAN_CFG4_2_ARMENDIAN_CFG4_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG4_2_ARMENDIAN_CFG4_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG4_2_ARMENDIAN_CFG4_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG4_2_ARMENDIAN_CFG4_RSVD2_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_ARMENDIAN_CFG4_2_ARMENDIAN_CFG4_RSVD2_SHIFT (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG4_2_ARMENDIAN_CFG4_RSVD2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG4_2_RESETVAL (0x00000000u)

/* armendian_cfg5_0 */

#define CSL_BOOTCFG_ARMENDIAN_CFG5_0_ARMENDIAN_CFG5_BASEADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARMENDIAN_CFG5_0_ARMENDIAN_CFG5_BASEADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARMENDIAN_CFG5_0_ARMENDIAN_CFG5_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG5_0_ARMENDIAN_CFG5_RSVD0_MASK (0x000000FFu)
#define CSL_BOOTCFG_ARMENDIAN_CFG5_0_ARMENDIAN_CFG5_RSVD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG5_0_ARMENDIAN_CFG5_RSVD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG5_0_RESETVAL (0x00000000u)

/* armendian_cfg5_1 */

#define CSL_BOOTCFG_ARMENDIAN_CFG5_1_ARMENDIAN_CFG5_BASEADDR_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARMENDIAN_CFG5_1_ARMENDIAN_CFG5_BASEADDR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG5_1_ARMENDIAN_CFG5_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG5_1_ARMENDIAN_CFG5_RSVD1_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_ARMENDIAN_CFG5_1_ARMENDIAN_CFG5_RSVD1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_ARMENDIAN_CFG5_1_ARMENDIAN_CFG5_RSVD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG5_1_RESETVAL (0x00000000u)

/* armendian_cfg5_2 */

#define CSL_BOOTCFG_ARMENDIAN_CFG5_2_ARMENDIAN_CFG5_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG5_2_ARMENDIAN_CFG5_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG5_2_ARMENDIAN_CFG5_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG5_2_ARMENDIAN_CFG5_RSVD2_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_ARMENDIAN_CFG5_2_ARMENDIAN_CFG5_RSVD2_SHIFT (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG5_2_ARMENDIAN_CFG5_RSVD2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG5_2_RESETVAL (0x00000000u)

/* armendian_cfg6_0 */

#define CSL_BOOTCFG_ARMENDIAN_CFG6_0_ARMENDIAN_CFG6_BASEADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARMENDIAN_CFG6_0_ARMENDIAN_CFG6_BASEADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARMENDIAN_CFG6_0_ARMENDIAN_CFG6_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG6_0_ARMENDIAN_CFG6_RSVD0_MASK (0x000000FFu)
#define CSL_BOOTCFG_ARMENDIAN_CFG6_0_ARMENDIAN_CFG6_RSVD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG6_0_ARMENDIAN_CFG6_RSVD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG6_0_RESETVAL (0x00000000u)

/* armendian_cfg6_1 */

#define CSL_BOOTCFG_ARMENDIAN_CFG6_1_ARMENDIAN_CFG6_BASEADDR_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARMENDIAN_CFG6_1_ARMENDIAN_CFG6_BASEADDR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG6_1_ARMENDIAN_CFG6_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG6_1_ARMENDIAN_CFG6_RSVD1_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_ARMENDIAN_CFG6_1_ARMENDIAN_CFG6_RSVD1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_ARMENDIAN_CFG6_1_ARMENDIAN_CFG6_RSVD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG6_1_RESETVAL (0x00000000u)

/* armendian_cfg6_2 */

#define CSL_BOOTCFG_ARMENDIAN_CFG6_2_ARMENDIAN_CFG6_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG6_2_ARMENDIAN_CFG6_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG6_2_ARMENDIAN_CFG6_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG6_2_ARMENDIAN_CFG6_RSVD2_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_ARMENDIAN_CFG6_2_ARMENDIAN_CFG6_RSVD2_SHIFT (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG6_2_ARMENDIAN_CFG6_RSVD2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG6_2_RESETVAL (0x00000000u)

/* armendian_cfg7_0 */

#define CSL_BOOTCFG_ARMENDIAN_CFG7_0_ARMENDIAN_CFG7_BASEADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARMENDIAN_CFG7_0_ARMENDIAN_CFG7_BASEADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARMENDIAN_CFG7_0_ARMENDIAN_CFG7_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG7_0_ARMENDIAN_CFG7_RSVD0_MASK (0x000000FFu)
#define CSL_BOOTCFG_ARMENDIAN_CFG7_0_ARMENDIAN_CFG7_RSVD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG7_0_ARMENDIAN_CFG7_RSVD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG7_0_RESETVAL (0x00000000u)

/* armendian_cfg7_1 */

#define CSL_BOOTCFG_ARMENDIAN_CFG7_1_ARMENDIAN_CFG7_BASEADDR_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARMENDIAN_CFG7_1_ARMENDIAN_CFG7_BASEADDR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG7_1_ARMENDIAN_CFG7_BASEADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG7_1_ARMENDIAN_CFG7_RSVD1_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_ARMENDIAN_CFG7_1_ARMENDIAN_CFG7_RSVD1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_ARMENDIAN_CFG7_1_ARMENDIAN_CFG7_RSVD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG7_1_RESETVAL (0x00000000u)

/* armendian_cfg7_2 */

#define CSL_BOOTCFG_ARMENDIAN_CFG7_2_ARMENDIAN_CFG7_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG7_2_ARMENDIAN_CFG7_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMENDIAN_CFG7_2_ARMENDIAN_CFG7_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG7_2_ARMENDIAN_CFG7_RSVD2_MASK (0xFFFFFFFEu)
#define CSL_BOOTCFG_ARMENDIAN_CFG7_2_ARMENDIAN_CFG7_RSVD2_SHIFT (0x00000001u)
#define CSL_BOOTCFG_ARMENDIAN_CFG7_2_ARMENDIAN_CFG7_RSVD2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMENDIAN_CFG7_2_RESETVAL (0x00000000u)

/* spare_2 */

#define CSL_BOOTCFG_SPARE_2_SPARE_2_OUT_MASK (0x7FFFFFFFu)
#define CSL_BOOTCFG_SPARE_2_SPARE_2_OUT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_2_SPARE_2_OUT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_2_SPARE_2_PULSE_MASK (0x80000000u)
#define CSL_BOOTCFG_SPARE_2_SPARE_2_PULSE_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_SPARE_2_SPARE_2_PULSE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_2_RESETVAL     (0x00000000u)

/* spare_3 */

#define CSL_BOOTCFG_SPARE_3_SPARE_3_OUT_MASK (0x7FFFFFFFu)
#define CSL_BOOTCFG_SPARE_3_SPARE_3_OUT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_3_SPARE_3_OUT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_3_SPARE_3_PULSE_MASK (0x80000000u)
#define CSL_BOOTCFG_SPARE_3_SPARE_3_PULSE_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_SPARE_3_SPARE_3_PULSE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_3_RESETVAL     (0x00000000u)

/* spare_4 */

#define CSL_BOOTCFG_SPARE_4_SPARE_4_OUT_MASK (0x7FFFFFFFu)
#define CSL_BOOTCFG_SPARE_4_SPARE_4_OUT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_4_SPARE_4_OUT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_4_SPARE_4_PULSE_MASK (0x80000000u)
#define CSL_BOOTCFG_SPARE_4_SPARE_4_PULSE_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_SPARE_4_SPARE_4_PULSE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_4_RESETVAL     (0x00000000u)

/* spare_5 */

#define CSL_BOOTCFG_SPARE_5_SPARE_5_OUT_MASK (0x7FFFFFFFu)
#define CSL_BOOTCFG_SPARE_5_SPARE_5_OUT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_5_SPARE_5_OUT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_5_SPARE_5_PULSE_MASK (0x80000000u)
#define CSL_BOOTCFG_SPARE_5_SPARE_5_PULSE_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_SPARE_5_SPARE_5_PULSE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_5_RESETVAL     (0x00000000u)

/* spare_6 */

#define CSL_BOOTCFG_SPARE_6_SPARE_6_OUT_MASK (0x7FFFFFFFu)
#define CSL_BOOTCFG_SPARE_6_SPARE_6_OUT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_6_SPARE_6_OUT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_6_SPARE_6_PULSE_MASK (0x80000000u)
#define CSL_BOOTCFG_SPARE_6_SPARE_6_PULSE_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_SPARE_6_SPARE_6_PULSE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_6_RESETVAL     (0x00000000u)

/* spare_7 */

#define CSL_BOOTCFG_SPARE_7_SPARE_7_OUT_MASK (0x7FFFFFFFu)
#define CSL_BOOTCFG_SPARE_7_SPARE_7_OUT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_7_SPARE_7_OUT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_7_SPARE_7_PULSE_MASK (0x80000000u)
#define CSL_BOOTCFG_SPARE_7_SPARE_7_PULSE_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_SPARE_7_SPARE_7_PULSE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_7_RESETVAL     (0x00000000u)

/* spare_8 */

#define CSL_BOOTCFG_SPARE_8_SPARE_8_IN_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE_8_SPARE_8_IN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_8_SPARE_8_IN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_8_RESETVAL     (0x00000000u)

/* spare_9 */

#define CSL_BOOTCFG_SPARE_9_SPARE_9_IN_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE_9_SPARE_9_IN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_9_SPARE_9_IN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_9_RESETVAL     (0x00000000u)

/* spare_10 */

#define CSL_BOOTCFG_SPARE_10_SPARE_10_IN_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE_10_SPARE_10_IN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_10_SPARE_10_IN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_10_RESETVAL    (0x00000000u)

/* spare_11 */

#define CSL_BOOTCFG_SPARE_11_SPARE_11_IN_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE_11_SPARE_11_IN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_11_SPARE_11_IN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_11_RESETVAL    (0x00000000u)

/* spare_12 */

#define CSL_BOOTCFG_SPARE_12_SPARE_12_IN_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE_12_SPARE_12_IN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_12_SPARE_12_IN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_12_RESETVAL    (0x00000000u)

/* spare_13 */

#define CSL_BOOTCFG_SPARE_13_SPARE_13_IN_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE_13_SPARE_13_IN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_13_SPARE_13_IN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_13_RESETVAL    (0x00000000u)

/* spare_14 */

#define CSL_BOOTCFG_SPARE_14_SPARE_14_IN_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE_14_SPARE_14_IN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_14_SPARE_14_IN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_14_RESETVAL    (0x00000000u)

/* spare_15 */

#define CSL_BOOTCFG_SPARE_15_SPARE_15_IN_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE_15_SPARE_15_IN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_15_SPARE_15_IN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_15_RESETVAL    (0x00000000u)

/* pin_muxctl0 */

#define CSL_BOOTCFG_PIN_MUXCTL0_AVSIF_SEL_MASK (0x00000001u)
#define CSL_BOOTCFG_PIN_MUXCTL0_AVSIF_SEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PIN_MUXCTL0_AVSIF_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PIN_MUXCTL0_DFESYNC_RP1_SEL_MASK (0x00000002u)
#define CSL_BOOTCFG_PIN_MUXCTL0_DFESYNC_RP1_SEL_SHIFT (0x00000001u)
#define CSL_BOOTCFG_PIN_MUXCTL0_DFESYNC_RP1_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PIN_MUXCTL0_UART01_SPI2CS_SEL_MASK (0x00000004u)
#define CSL_BOOTCFG_PIN_MUXCTL0_UART01_SPI2CS_SEL_SHIFT (0x00000002u)
#define CSL_BOOTCFG_PIN_MUXCTL0_UART01_SPI2CS_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PIN_MUXCTL0_PIN_MUXCTL0A_RSVD_MASK (0x00000008u)
#define CSL_BOOTCFG_PIN_MUXCTL0_PIN_MUXCTL0A_RSVD_SHIFT (0x00000003u)
#define CSL_BOOTCFG_PIN_MUXCTL0_PIN_MUXCTL0A_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PIN_MUXCTL0_UART2_EMIFA_SEL_MASK (0x00000030u)
#define CSL_BOOTCFG_PIN_MUXCTL0_UART2_EMIFA_SEL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_PIN_MUXCTL0_UART2_EMIFA_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PIN_MUXCTL0_UART3_EMIFA_SEL_MASK (0x000000C0u)
#define CSL_BOOTCFG_PIN_MUXCTL0_UART3_EMIFA_SEL_SHIFT (0x00000006u)
#define CSL_BOOTCFG_PIN_MUXCTL0_UART3_EMIFA_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PIN_MUXCTL0_PIN_MUXCTL0_RSVD_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_PIN_MUXCTL0_PIN_MUXCTL0_RSVD_SHIFT (0x00000008u)
#define CSL_BOOTCFG_PIN_MUXCTL0_PIN_MUXCTL0_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PIN_MUXCTL0_RESETVAL (0x00000000u)

/* pin_muxctl1 */

#define CSL_BOOTCFG_PIN_MUXCTL1_GPIO_SPI2CS_SEL_MASK (0x0000000Fu)
#define CSL_BOOTCFG_PIN_MUXCTL1_GPIO_SPI2CS_SEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PIN_MUXCTL1_GPIO_SPI2CS_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PIN_MUXCTL1_GPIO_TIMIO_SEL_MASK (0x0000FFF0u)
#define CSL_BOOTCFG_PIN_MUXCTL1_GPIO_TIMIO_SEL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_PIN_MUXCTL1_GPIO_TIMIO_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PIN_MUXCTL1_GPIO_EMU_SEL_MASK (0xFFFF0000u)
#define CSL_BOOTCFG_PIN_MUXCTL1_GPIO_EMU_SEL_SHIFT (0x00000010u)
#define CSL_BOOTCFG_PIN_MUXCTL1_GPIO_EMU_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PIN_MUXCTL1_RESETVAL (0x00000000u)

/* pin_muxctl2 */

#define CSL_BOOTCFG_PIN_MUXCTL2_GPIO_EMIFA_SEL_MASK (0x0000FFFFu)
#define CSL_BOOTCFG_PIN_MUXCTL2_GPIO_EMIFA_SEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PIN_MUXCTL2_GPIO_EMIFA_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PIN_MUXCTL2_GPIO_DFEIO_SEL_MASK (0xFFFF0000u)
#define CSL_BOOTCFG_PIN_MUXCTL2_GPIO_DFEIO_SEL_SHIFT (0x00000010u)
#define CSL_BOOTCFG_PIN_MUXCTL2_GPIO_DFEIO_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PIN_MUXCTL2_RESETVAL (0x00000000u)

/* dfe_clkdiv_ctl */

#define CSL_BOOTCFG_DFE_CLKDIV_CTL_DIV_MODE_MASK (0x00000003u)
#define CSL_BOOTCFG_DFE_CLKDIV_CTL_DIV_MODE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DFE_CLKDIV_CTL_DIV_MODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFE_CLKDIV_CTL_RESETVAL (0x00000000u)

/* dfe_clksync_ctl */

#define CSL_BOOTCFG_DFE_CLKSYNC_CTL_SYNC_EN_MASK (0x00000001u)
#define CSL_BOOTCFG_DFE_CLKSYNC_CTL_SYNC_EN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DFE_CLKSYNC_CTL_SYNC_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFE_CLKSYNC_CTL_RESETVAL (0x00000000u)

/* iqn_ailrstiso_ctl */

#define CSL_BOOTCFG_IQN_AILRSTISO_CTL_AILRSTISOEN_MASK (0x00000001u)
#define CSL_BOOTCFG_IQN_AILRSTISO_CTL_AILRSTISOEN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IQN_AILRSTISO_CTL_AILRSTISOEN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IQN_AILRSTISO_CTL_SGMIIRSTISOEN_MASK (0x00000002u)
#define CSL_BOOTCFG_IQN_AILRSTISO_CTL_SGMIIRSTISOEN_SHIFT (0x00000001u)
#define CSL_BOOTCFG_IQN_AILRSTISO_CTL_SGMIIRSTISOEN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IQN_AILRSTISO_CTL_RESETVAL (0x00000000u)

/* iqn_rstreq_ctl */

#define CSL_BOOTCFG_IQN_RSTREQ_CTL_EN_MASK (0x00000002u)
#define CSL_BOOTCFG_IQN_RSTREQ_CTL_EN_SHIFT (0x00000001u)
#define CSL_BOOTCFG_IQN_RSTREQ_CTL_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IQN_RSTREQ_CTL_EVTSTAT_MASK (0x00000010u)
#define CSL_BOOTCFG_IQN_RSTREQ_CTL_EVTSTAT_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IQN_RSTREQ_CTL_EVTSTAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IQN_RSTREQ_CTL_EVTSTATCLR_MASK (0x00000200u)
#define CSL_BOOTCFG_IQN_RSTREQ_CTL_EVTSTATCLR_SHIFT (0x00000009u)
#define CSL_BOOTCFG_IQN_RSTREQ_CTL_EVTSTATCLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_IQN_RSTREQ_CTL_RESETVAL (0x00000000u)

/* chip_misc */

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_QM_PRIOR_MASK (0x00000007u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_QM_PRIOR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_QM_PRIOR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RSVD0_MASK (0x00000FF8u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RSVD0_SHIFT (0x00000003u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RSVD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_MSMC_BLOCK_PARITY_RST_MASK (0x00001000u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_MSMC_BLOCK_PARITY_RST_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_MSMC_BLOCK_PARITY_RST_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RACA_DISABLE_MASK (0x00002000u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RACA_DISABLE_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RACA_DISABLE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RSVD1_MASK (0x0003C000u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RSVD1_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RSVD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_USB_PME_EN_MASK (0x00040000u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_USB_PME_EN_SHIFT (0x00000012u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_USB_PME_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_RST_ISO_IP_RST_BLK_MASK (0x03F80000u)
#define CSL_BOOTCFG_CHIP_MISC_RST_ISO_IP_RST_BLK_SHIFT (0x00000013u)
#define CSL_BOOTCFG_CHIP_MISC_RST_ISO_IP_RST_BLK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_EFUSE_REDUND_EN_MASK (0x04000000u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_EFUSE_REDUND_EN_SHIFT (0x0000001Au)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_EFUSE_REDUND_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_EFUSE_ACTUAL_EN_MASK (0x08000000u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_EFUSE_ACTUAL_EN_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_EFUSE_ACTUAL_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RSVD2_MASK (0xF0000000u)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RSVD2_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_CHIP_MISC_CHIP_MISC_RSVD2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_RESETVAL   (0x00000000u)

/* spare_0 */

#define CSL_BOOTCFG_SPARE_0_SPARE_0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE_0_SPARE_0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_0_SPARE_0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_0_RESETVAL     (0x00000000u)

/* spare_1 */

#define CSL_BOOTCFG_SPARE_1_SPARE_1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE_1_SPARE_1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SPARE_1_SPARE_1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE_1_RESETVAL     (0x00000000u)

/* sys_endian */

#define CSL_BOOTCFG_SYS_ENDIAN_SYS_ENDIAN_MASK (0x00000001u)
#define CSL_BOOTCFG_SYS_ENDIAN_SYS_ENDIAN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SYS_ENDIAN_SYS_ENDIAN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SYS_ENDIAN_RESETVAL  (0x00000000u)

/* plllock_pinctl */

#define CSL_BOOTCFG_PLLLOCK_PINCTL_MAIN_PLL_MASK (0x00000001u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_MAIN_PLL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_MAIN_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_PLL_MASK (0x00000002u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_PLL_SHIFT (0x00000001u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_PA_PLL_MASK (0x00000008u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_PA_PLL_SHIFT (0x00000003u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_PA_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_ARM_PLL_MASK (0x00000010u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_ARM_PLL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_ARM_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_DFE_PLL_MASK (0x00000020u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DFE_PLL_SHIFT (0x00000005u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DFE_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_SGMII_PLL_MASK (0x00000200u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_SGMII_PLL_SHIFT (0x00000009u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_SGMII_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_CSISC2_3_PLL_MASK (0x00000400u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_CSISC2_3_PLL_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_CSISC2_3_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_USB_PLL_MASK (0x00000800u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_USB_PLL_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_USB_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA0_PLL_MASK (0x00004000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA0_PLL_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA0_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA1_PLL_MASK (0x00008000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA1_PLL_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA1_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA2_PLL_MASK (0x00010000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA2_PLL_SHIFT (0x00000010u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA2_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA3_PLL_MASK (0x00020000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA3_PLL_SHIFT (0x00000011u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA3_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA4_PLL_MASK (0x00040000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA4_PLL_SHIFT (0x00000012u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA4_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA5_PLL_MASK (0x00080000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA5_PLL_SHIFT (0x00000013u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA5_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA6_PLL_MASK (0x00100000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA6_PLL_SHIFT (0x00000014u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA6_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA7_PLL_MASK (0x00200000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA7_PLL_SHIFT (0x00000015u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA7_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA8_PLL_MASK (0x00400000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA8_PLL_SHIFT (0x00000016u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DDR3A_DATA8_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_CSISC2_0_PLL_MASK (0x00800000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_CSISC2_0_PLL_SHIFT (0x00000017u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_CSISC2_0_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_CSISC2_1_PLL_MASK (0x01000000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_CSISC2_1_PLL_SHIFT (0x00000018u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_CSISC2_1_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_RESETVAL (0x00000000u)

/* plllock_stat */

#define CSL_BOOTCFG_PLLLOCK_STAT_MAIN_PLL_MASK (0x00000001u)
#define CSL_BOOTCFG_PLLLOCK_STAT_MAIN_PLL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_MAIN_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_PLL_MASK (0x00000002u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_PLL_SHIFT (0x00000001u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_PA_PLL_MASK (0x00000008u)
#define CSL_BOOTCFG_PLLLOCK_STAT_PA_PLL_SHIFT (0x00000003u)
#define CSL_BOOTCFG_PLLLOCK_STAT_PA_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_ARM_PLL_MASK (0x00000010u)
#define CSL_BOOTCFG_PLLLOCK_STAT_ARM_PLL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_PLLLOCK_STAT_ARM_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_DFE_PLL_MASK (0x00000020u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DFE_PLL_SHIFT (0x00000005u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DFE_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_SGMII_PLL_MASK (0x00000200u)
#define CSL_BOOTCFG_PLLLOCK_STAT_SGMII_PLL_SHIFT (0x00000009u)
#define CSL_BOOTCFG_PLLLOCK_STAT_SGMII_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_CSISC2_3_PLL_MASK (0x00000400u)
#define CSL_BOOTCFG_PLLLOCK_STAT_CSISC2_3_PLL_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_PLLLOCK_STAT_CSISC2_3_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_USB_PLL_MASK (0x00000800u)
#define CSL_BOOTCFG_PLLLOCK_STAT_USB_PLL_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_PLLLOCK_STAT_USB_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA0_PLL_MASK (0x00004000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA0_PLL_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA0_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA1_PLL_MASK (0x00008000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA1_PLL_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA1_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA2_PLL_MASK (0x00010000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA2_PLL_SHIFT (0x00000010u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA2_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA3_PLL_MASK (0x00020000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA3_PLL_SHIFT (0x00000011u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA3_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA4_PLL_MASK (0x00040000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA4_PLL_SHIFT (0x00000012u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA4_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA5_PLL_MASK (0x00080000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA5_PLL_SHIFT (0x00000013u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA5_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA6_PLL_MASK (0x00100000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA6_PLL_SHIFT (0x00000014u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA6_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA7_PLL_MASK (0x00200000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA7_PLL_SHIFT (0x00000015u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA7_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA8_PLL_MASK (0x00400000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA8_PLL_SHIFT (0x00000016u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_DATA8_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_CSISC2_0_PLL_MASK (0x00800000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_CSISC2_0_PLL_SHIFT (0x00000017u)
#define CSL_BOOTCFG_PLLLOCK_STAT_CSISC2_0_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_CSISC2_1_PLL_MASK (0x01000000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_CSISC2_1_PLL_SHIFT (0x00000018u)
#define CSL_BOOTCFG_PLLLOCK_STAT_CSISC2_1_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_RESETVAL (0x00000000u)

/* plllock_eval */

#define CSL_BOOTCFG_PLLLOCK_EVAL_MAIN_PLL_MASK (0x00000001u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_MAIN_PLL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_MAIN_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_PLL_MASK (0x00000002u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_PLL_SHIFT (0x00000001u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_PA_PLL_MASK (0x00000008u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_PA_PLL_SHIFT (0x00000003u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_PA_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_ARM_PLL_MASK (0x00000010u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_ARM_PLL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_ARM_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_DFE_PLL_MASK (0x00000020u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DFE_PLL_SHIFT (0x00000005u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DFE_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_SGMII_PLL_MASK (0x00000200u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_SGMII_PLL_SHIFT (0x00000009u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_SGMII_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_CSISC2_3_PLL_MASK (0x00000400u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_CSISC2_3_PLL_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_PLLLOCK_EVAL_CSISC2_3_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_USB_PLL_MASK (0x00000800u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_USB_PLL_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_PLLLOCK_EVAL_USB_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA0_PLL_MASK (0x00004000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA0_PLL_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA0_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA1_PLL_MASK (0x00008000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA1_PLL_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA1_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA2_PLL_MASK (0x00010000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA2_PLL_SHIFT (0x00000010u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA2_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA3_PLL_MASK (0x00020000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA3_PLL_SHIFT (0x00000011u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA3_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA4_PLL_MASK (0x00040000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA4_PLL_SHIFT (0x00000012u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA4_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA5_PLL_MASK (0x00080000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA5_PLL_SHIFT (0x00000013u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA5_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA6_PLL_MASK (0x00100000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA6_PLL_SHIFT (0x00000014u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA6_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA7_PLL_MASK (0x00200000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA7_PLL_SHIFT (0x00000015u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA7_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA8_PLL_MASK (0x00400000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA8_PLL_SHIFT (0x00000016u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_DATA8_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_CSISC2_0_PLL_MASK (0x00800000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_CSISC2_0_PLL_SHIFT (0x00000017u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_CSISC2_0_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_CSISC2_1_PLL_MASK (0x01000000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_CSISC2_1_PLL_SHIFT (0x00000018u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_CSISC2_1_PLL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_RESETVAL (0x00000000u)

/* pllclksel_stat */

#define CSL_BOOTCFG_PLLCLKSEL_STAT_CORECLKSEL_MASK (0x00000003u)
#define CSL_BOOTCFG_PLLCLKSEL_STAT_CORECLKSEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PLLCLKSEL_STAT_CORECLKSEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLCLKSEL_STAT_DFECLKSEL_MASK (0x00000004u)
#define CSL_BOOTCFG_PLLCLKSEL_STAT_DFECLKSEL_SHIFT (0x00000002u)
#define CSL_BOOTCFG_PLLCLKSEL_STAT_DFECLKSEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLCLKSEL_STAT_RESETVAL (0x00000000u)

/* tsrxclk_pinctl */

#define CSL_BOOTCFG_TSRXCLK_PINCTL_TSRXCLKOUTSEL_MASK (0x00000007u)
#define CSL_BOOTCFG_TSRXCLK_PINCTL_TSRXCLKOUTSEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TSRXCLK_PINCTL_TSRXCLKOUTSEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TSRXCLK_PINCTL_TSRXCLK_RSVD_MASK (0xFFFFFFF8u)
#define CSL_BOOTCFG_TSRXCLK_PINCTL_TSRXCLK_RSVD_SHIFT (0x00000003u)
#define CSL_BOOTCFG_TSRXCLK_PINCTL_TSRXCLK_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TSRXCLK_PINCTL_RESETVAL (0x00000000u)

/* led_core_passdone0 */

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D0_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D0_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D1_MASK (0x00000020u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D1_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D2_MASK (0x00000200u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D2_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D3_MASK (0x00002000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D3_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_D3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I0_MASK (0x00000004u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I0_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I1_MASK (0x00000040u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I1_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I2_MASK (0x00000400u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I2_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I3_MASK (0x00004000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I3_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_I3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L0_MASK (0x00000008u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L0_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L1_MASK (0x00000080u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L1_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L2_MASK (0x00000800u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L2_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L3_MASK (0x00008000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L3_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_L3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_LED_GEM_PASSDONE1_RSVD_MASK (0xFFFF0000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_LED_GEM_PASSDONE1_RSVD_SHIFT (0x00000010u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_LED_GEM_PASSDONE1_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P0_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P1_MASK (0x00000010u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P2_MASK (0x00000100u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P2_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P3_MASK (0x00001000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P3_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_P3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_RESETVAL (0x00000000u)

/* led_core_passdone1 */

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D8_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D8_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D9_MASK (0x00000020u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D9_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_D9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I8_MASK (0x00000004u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I8_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I9_MASK (0x00000040u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I9_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_I9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L8_MASK (0x00000008u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L8_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L9_MASK (0x00000080u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L9_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_L9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_LED_GEM_PASSDONE2_RSVD_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_LED_GEM_PASSDONE2_RSVD_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_LED_GEM_PASSDONE2_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P8_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P8_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P9_MASK (0x00000010u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P9_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_P9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_RESETVAL (0x00000000u)

/* led_arm_bootaddr */

#define CSL_BOOTCFG_LED_ARM_BOOTADDR_LED_ARM_BOOTADDR_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_LED_ARM_BOOTADDR_LED_ARM_BOOTADDR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_ARM_BOOTADDR_LED_ARM_BOOTADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_ARM_BOOTADDR_RESETVAL (0x00000000u)

/* led_gpio_clr */

#define CSL_BOOTCFG_LED_GPIO_CLR_LED_GPIO_SRC_CLR_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_LED_GPIO_CLR_LED_GPIO_SRC_CLR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_GPIO_CLR_LED_GPIO_SRC_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_GPIO_CLR_RESETVAL (0x00000000u)

/* led_gpio_clr1 */

#define CSL_BOOTCFG_LED_GPIO_CLR1_LED_GPIO_SRC_CLR1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_LED_GPIO_CLR1_LED_GPIO_SRC_CLR1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_GPIO_CLR1_LED_GPIO_SRC_CLR1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_GPIO_CLR1_RESETVAL (0x00000000u)

/* led_gpio1 */

#define CSL_BOOTCFG_LED_GPIO1_LED_GPIO_SRC_SET1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_LED_GPIO1_LED_GPIO_SRC_SET1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_GPIO1_LED_GPIO_SRC_SET1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_GPIO1_RESETVAL   (0x00000000u)

/* led_gpio2 */

#define CSL_BOOTCFG_LED_GPIO2_LED_GPIO_SRC_SET2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_LED_GPIO2_LED_GPIO_SRC_SET2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_GPIO2_LED_GPIO_SRC_SET2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_GPIO2_RESETVAL   (0x00000000u)

/* led_plllock0 */

#define CSL_BOOTCFG_LED_PLLLOCK0_GEM0_CODE_LOADED_MASK (0x00000004u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM0_CODE_LOADED_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM0_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_GEM0_EXE_OK_MASK (0x00000008u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM0_EXE_OK_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM0_EXE_OK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_GEM1_CODE_LOADED_MASK (0x00000010u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM1_CODE_LOADED_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM1_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_GEM1_EXE_OK_MASK (0x00000020u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM1_EXE_OK_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM1_EXE_OK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_GEM2_CODE_LOADED_MASK (0x00000040u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM2_CODE_LOADED_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM2_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_GEM2_EXE_OK_MASK (0x00000080u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM2_EXE_OK_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM2_EXE_OK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_GEM3_CODE_LOADED_MASK (0x00000100u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM3_CODE_LOADED_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM3_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_GEM3_EXE_OK_MASK (0x00000200u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM3_EXE_OK_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM3_EXE_OK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_GEM_GENERAL_MASK (0x7FFC0000u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM_GENERAL_SHIFT (0x00000012u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM_GENERAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_GEM_SUSP_CTL_MASK (0x80000000u)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM_SUSP_CTL_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_LED_PLLLOCK0_GEM_SUSP_CTL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_PLLLOCK_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_PLLLOCK0_PLLLOCK_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_PLLLOCK0_PLLLOCK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_STICKY_EN_LOCK_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_PLLLOCK0_STICKY_EN_LOCK_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_PLLLOCK0_STICKY_EN_LOCK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK0_RESETVAL (0x00000000u)

/* led_plllock1 */

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE0_CODE_LOADED_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE0_CODE_LOADED_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE0_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE0_EXE_OK_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE0_EXE_OK_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE0_EXE_OK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE1_CODE_LOADED_MASK (0x00000004u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE1_CODE_LOADED_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE1_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE1_EXE_OK_MASK (0x00000008u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE1_EXE_OK_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE1_EXE_OK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE2_CODE_LOADED_MASK (0x00000010u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE2_CODE_LOADED_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE2_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE2_EXE_OK_MASK (0x00000020u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE2_EXE_OK_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE2_EXE_OK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE3_CODE_LOADED_MASK (0x00000040u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE3_CODE_LOADED_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE3_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE3_EXE_OK_MASK (0x00000080u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE3_EXE_OK_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE3_EXE_OK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE8_CODE_LOADED_MASK (0x00010000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE8_CODE_LOADED_SHIFT (0x00000010u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE8_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE8_EXE_OK_MASK (0x00020000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE8_EXE_OK_SHIFT (0x00000011u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE8_EXE_OK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE9_CODE_LOADED_MASK (0x00040000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE9_CODE_LOADED_SHIFT (0x00000012u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE9_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_CORE9_EXE_OK_MASK (0x00080000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE9_EXE_OK_SHIFT (0x00000013u)
#define CSL_BOOTCFG_LED_PLLLOCK1_CORE9_EXE_OK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_RESETVAL (0x00000000u)

/* led_chip_passdone */

#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_DONE_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_DONE_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_DONE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_PASS_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_PASS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_PASS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CHIP_PASSDONE_LED_CHIP_PASSDONE_RSVD_MASK (0xFFFFFFFCu)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_LED_CHIP_PASSDONE_RSVD_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_LED_CHIP_PASSDONE_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CHIP_PASSDONE_RESETVAL (0x00000000u)

/* tdiode */

#define CSL_BOOTCFG_TDIODE_TDIODE_MASK   (0xFFFFFFFFu)
#define CSL_BOOTCFG_TDIODE_TDIODE_SHIFT  (0x00000000u)
#define CSL_BOOTCFG_TDIODE_TDIODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TDIODE_RESETVAL      (0x00000000u)

/* margin0 */

#define CSL_BOOTCFG_MARGIN0_BTCFG_MARGIN_EN_MASK (0x80000000u)
#define CSL_BOOTCFG_MARGIN0_BTCFG_MARGIN_EN_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_MARGIN0_BTCFG_MARGIN_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN0_DFTWRITE0_MASK (0x000007FFu)
#define CSL_BOOTCFG_MARGIN0_DFTWRITE0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MARGIN0_DFTWRITE0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN0_DFTWRITE1_MASK (0x003FF800u)
#define CSL_BOOTCFG_MARGIN0_DFTWRITE1_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_MARGIN0_DFTWRITE1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN0_RESETVAL     (0x00000000u)

/* margin1 */

#define CSL_BOOTCFG_MARGIN1_DFTREAD0_MASK (0x000007FFu)
#define CSL_BOOTCFG_MARGIN1_DFTREAD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MARGIN1_DFTREAD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN1_DFTREAD1_MASK (0x003FF800u)
#define CSL_BOOTCFG_MARGIN1_DFTREAD1_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_MARGIN1_DFTREAD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN1_RESETVAL     (0x00000000u)

/* margin2 */

#define CSL_BOOTCFG_MARGIN2_DFTREAD2_MASK (0x000007FFu)
#define CSL_BOOTCFG_MARGIN2_DFTREAD2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MARGIN2_DFTREAD2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN2_DFTREAD3_MASK (0x003FF800u)
#define CSL_BOOTCFG_MARGIN2_DFTREAD3_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_MARGIN2_DFTREAD3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN2_RESETVAL     (0x00000000u)

/* int_spare0 */

#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_SELECT_MASK (0x00000007u)
#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_SELECT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_SELECT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_EN_MASK (0x00000008u)
#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_EN_SHIFT (0x00000003u)
#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_DONE_MASK (0x000000F0u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_DONE_SHIFT (0x00000004u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_DONE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_ERR_MASK (0x00000F00u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_ERR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_ERR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_EFC_ERR_MASK (0x00001000u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_ERR_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_INT_SPARE0_EFC_ERR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_EFC_INFO_MASK (0x00002000u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_INFO_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_INT_SPARE0_EFC_INFO_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_SPARE_OUT_MASK (0xFFFFC000u)
#define CSL_BOOTCFG_INT_SPARE0_SPARE_OUT_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_INT_SPARE0_SPARE_OUT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_RESETVAL  (0x00000000u)

/* int_spare1 */

#define CSL_BOOTCFG_INT_SPARE1_SPARE1_OUT_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_INT_SPARE1_SPARE1_OUT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_INT_SPARE1_SPARE1_OUT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE1_RESETVAL  (0x00000000u)

/* led_misc_ctl */

#define CSL_BOOTCFG_LED_MISC_CTL_LED_DSPBOOTADDR_RSTCTL_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_MISC_CTL_LED_DSPBOOTADDR_RSTCTL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_MISC_CTL_LED_DSPBOOTADDR_RSTCTL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_MISC_CTL_RESETVAL (0x00000000u)

/* chip_misc_ctl1 */

#define CSL_BOOTCFG_CHIP_MISC_CTL1_RSVD0_MASK (0x00000007u)
#define CSL_BOOTCFG_CHIP_MISC_CTL1_RSVD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_CHIP_MISC_CTL1_RSVD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CTL1_CGEM_L2_RD_LAT_MASK (0x00000078u)
#define CSL_BOOTCFG_CHIP_MISC_CTL1_CGEM_L2_RD_LAT_SHIFT (0x00000003u)
#define CSL_BOOTCFG_CHIP_MISC_CTL1_CGEM_L2_RD_LAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CTL1_CGEM_L2_ACS_LAT_MASK (0x00000780u)
#define CSL_BOOTCFG_CHIP_MISC_CTL1_CGEM_L2_ACS_LAT_SHIFT (0x00000007u)
#define CSL_BOOTCFG_CHIP_MISC_CTL1_CGEM_L2_ACS_LAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CTL1_DDR3_PSC_LOCK_N_MASK (0x00000800u)
#define CSL_BOOTCFG_CHIP_MISC_CTL1_DDR3_PSC_LOCK_N_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_CHIP_MISC_CTL1_DDR3_PSC_LOCK_N_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CTL1_TETRIS_PBIST_EN_MASK (0x00001000u)
#define CSL_BOOTCFG_CHIP_MISC_CTL1_TETRIS_PBIST_EN_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_CHIP_MISC_CTL1_TETRIS_PBIST_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CTL1_TETRIS_PLL_EN_MASK (0x00002000u)
#define CSL_BOOTCFG_CHIP_MISC_CTL1_TETRIS_PLL_EN_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_CHIP_MISC_CTL1_TETRIS_PLL_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC_CTL1_RESETVAL (0x00000000u)

/* obsclk_ctl */

#define CSL_BOOTCFG_OBSCLK_CTL_PLL_OBSCLK_SEL_MASK (0x00000007u)
#define CSL_BOOTCFG_OBSCLK_CTL_PLL_OBSCLK_SEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_OBSCLK_CTL_PLL_OBSCLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_EN_MASK (0x00000008u)
#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_EN_SHIFT (0x00000003u)
#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_ARM_PLL_OBSCLK_EN_MASK (0x00000010u)
#define CSL_BOOTCFG_OBSCLK_CTL_ARM_PLL_OBSCLK_EN_SHIFT (0x00000004u)
#define CSL_BOOTCFG_OBSCLK_CTL_ARM_PLL_OBSCLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_DDR3_PLL_OBSCLK_EN_MASK (0x00000020u)
#define CSL_BOOTCFG_OBSCLK_CTL_DDR3_PLL_OBSCLK_EN_SHIFT (0x00000005u)
#define CSL_BOOTCFG_OBSCLK_CTL_DDR3_PLL_OBSCLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_EN_MASK (0x00000040u)
#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_EN_SHIFT (0x00000006u)
#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_DFE_PLL_OBSCLK_SEL0_MASK (0x00070000u)
#define CSL_BOOTCFG_OBSCLK_CTL_DFE_PLL_OBSCLK_SEL0_SHIFT (0x00000010u)
#define CSL_BOOTCFG_OBSCLK_CTL_DFE_PLL_OBSCLK_SEL0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_DFE_PLL_OBSCLK_EN0_MASK (0x00080000u)
#define CSL_BOOTCFG_OBSCLK_CTL_DFE_PLL_OBSCLK_EN0_SHIFT (0x00000013u)
#define CSL_BOOTCFG_OBSCLK_CTL_DFE_PLL_OBSCLK_EN0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_DFE_PLL_OBSCLK_SEL1_MASK (0x00700000u)
#define CSL_BOOTCFG_OBSCLK_CTL_DFE_PLL_OBSCLK_SEL1_SHIFT (0x00000014u)
#define CSL_BOOTCFG_OBSCLK_CTL_DFE_PLL_OBSCLK_SEL1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_DFE_PLL_OBSCLK_EN1_MASK (0x00800000u)
#define CSL_BOOTCFG_OBSCLK_CTL_DFE_PLL_OBSCLK_EN1_SHIFT (0x00000017u)
#define CSL_BOOTCFG_OBSCLK_CTL_DFE_PLL_OBSCLK_EN1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_RESETVAL  (0x00000000u)

/* int_disablestat */

#define CSL_BOOTCFG_INT_DISABLESTAT_ALLPD_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_INT_DISABLESTAT_ALLPD_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_INT_DISABLESTAT_ALLPD_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_DISABLESTAT_ALLMD_DIS_MASK (0x00000002u)
#define CSL_BOOTCFG_INT_DISABLESTAT_ALLMD_DIS_SHIFT (0x00000001u)
#define CSL_BOOTCFG_INT_DISABLESTAT_ALLMD_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_DISABLESTAT_DDR3A_DIS_MASK (0x00000004u)
#define CSL_BOOTCFG_INT_DISABLESTAT_DDR3A_DIS_SHIFT (0x00000002u)
#define CSL_BOOTCFG_INT_DISABLESTAT_DDR3A_DIS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_DISABLESTAT_RSVD_MASK (0x00000008u)
#define CSL_BOOTCFG_INT_DISABLESTAT_RSVD_SHIFT (0x00000003u)
#define CSL_BOOTCFG_INT_DISABLESTAT_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_DISABLESTAT_RESETVAL (0x00000000u)

/* efuse_rsvd0 */

#define CSL_BOOTCFG_EFUSE_RSVD0_RSVD_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_RSVD0_RSVD_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_RSVD0_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD0_RESETVAL (0x00000000u)

/* efuse_rsvd1 */

#define CSL_BOOTCFG_EFUSE_RSVD1_RSVD_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_RSVD1_RSVD_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_RSVD1_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD1_RESETVAL (0x00000000u)

/* efuse_rsvd2 */

#define CSL_BOOTCFG_EFUSE_RSVD2_ARM_SPEED_MASK (0x00000FFFu)
#define CSL_BOOTCFG_EFUSE_RSVD2_ARM_SPEED_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_RSVD2_ARM_SPEED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD2_RSVD_MASK (0x0000F000u)
#define CSL_BOOTCFG_EFUSE_RSVD2_RSVD_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_EFUSE_RSVD2_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD2_DEVICE_SPEED_MASK (0x0FFF0000u)
#define CSL_BOOTCFG_EFUSE_RSVD2_DEVICE_SPEED_SHIFT (0x00000010u)
#define CSL_BOOTCFG_EFUSE_RSVD2_DEVICE_SPEED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD2_RSVD1_MASK (0xF0000000u)
#define CSL_BOOTCFG_EFUSE_RSVD2_RSVD1_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_EFUSE_RSVD2_RSVD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD2_RESETVAL (0x00000000u)

/* efuse_rsvd3 */

#define CSL_BOOTCFG_EFUSE_RSVD3_RSVD_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_RSVD3_RSVD_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_RSVD3_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD3_RESETVAL (0x00000000u)

/* pwrswtch_wkup_mode0_0 */

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_0_PWRSWTCH_WKUP_MODE_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_0_PWRSWTCH_WKUP_MODE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_0_PWRSWTCH_WKUP_MODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_0_RESETVAL (0x00000000u)

/* pwrswtch_wkup_mode0_1 */

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_1_PWRSWTCH_WKUP_MODE_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_1_PWRSWTCH_WKUP_MODE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_1_PWRSWTCH_WKUP_MODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_1_RESETVAL (0x00000000u)

/* pwrswtch_wkup_mode1_0 */

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_0_PWRSWTCH_WKUP_MODE_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_0_PWRSWTCH_WKUP_MODE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_0_PWRSWTCH_WKUP_MODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_0_RESETVAL (0x00000000u)

/* pwrswtch_wkup_mode1_1 */

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_1_PWRSWTCH_WKUP_MODE_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_1_PWRSWTCH_WKUP_MODE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_1_PWRSWTCH_WKUP_MODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_1_RESETVAL (0x00000000u)

/* int_pin_muxctl */

#define CSL_BOOTCFG_INT_PIN_MUXCTL_PASS_DONE_SEL_MASK (0x00000001u)
#define CSL_BOOTCFG_INT_PIN_MUXCTL_PASS_DONE_SEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_INT_PIN_MUXCTL_PASS_DONE_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_PIN_MUXCTL_RESETVAL (0x00000000u)


#ifdef __cplusplus
}
#endif

#endif
